A new full CMOS SRAM cell structure

Kudoh, O.; Ooka, H.; Sakai, I.; Saitoh, M.; Ozaki, Josuke; Kikuchi, M.

doi:10.1109/iedm.1984.190643

Cited by 6 publications

(1 citation statement)

References 2 publications

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“…has gained popularity among circuit designers because of its stability, low power consumption and simple fabrication process[37,[138][139][140][141][142][143][144][145]. The 6T cell is made up of a flip-flop formed by two cross-coupled inverters (M1, M3 and M2, M4) and two pass-gatetransistors (M5 and M6).…”

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confidence: 99%

Design of low-voltage low-power nano-scale SRAMs

Tuan¹

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Static Random Access Memory (SRAM)-based cache is one of the most important components of state-of-the-art VLSI systems. It is responsible for increasing the speed of data flows, and hence the speed of the whole electronic system. SRAM is prevalently utilized in the design of modern microprocessors for bridging the widening divergence between the performances of the Central Processing Unit (CPU) and the Dynamic RAM (DRAM)-based main memory. This trend is accentuated by the never-ending market demand for sophisticated communication and multimedia applications, which require high-tech portable electronic gadgets with high-performance as the requisite feature. As the on-chip memory occupies a large portion of the chip area, the power dissipated within the memory, both active and standby, will become a dominant part of the chip's total power consumption. In view of the above, there is invariably an apparent urgency to address these two often-conflicting power and performance requirements. Our research focuses on SRAM cell design for ultra low-voltage ultra low-power applications. Two SRAM cell topologies have been proposed with an improved noise margin and hence can operate at very low supply voltages to save power. Our first proposal is a 10T SRAM cell design that has 4x read and lox leakage power reduction when compared to the conventional 6T design. The proposed cell has separate readwrite ports and hence its read noise margin is 31% higher than that of the conventional 6T design. We also proposed a special read scheme that accesses only one cell during read out and hence more than 98% of cell active current is saved (assuming that each row has 128 cells and operating frequency is 250 MHz). This hefty amount of power reduction is obtained at the cost of 33% cell area overhead and 23% of write-ability. Extensive simulations on two SRAM macros using a standard 65nm / 1V CMOS process showed that the total read power consumption of the proposed design has reduced to 25% of that of the conventional 6T design. It also has smaller write power consumption. More

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