This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a Content-Addressable-Memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 µs. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V ~ 0.6 V by the proposed CAM-assisted circuit. Index Terms-Bitline leakage equalization, content addressable memory, energy efficiency improvement, ultra-low voltage SRAM design I. INTRODUCTION TATE-OF-THE-ART DSP cores and advanced healthcare SoCs [1],[2] benefit from availability of on-chip SRAMs with substantially reduced power dissipation and improved energy efficiency. Integrated SRAMs play a crucial role in providing the required density, performance, power, and energy Manuscript

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This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the power reduction of 5.5× compared with the conventional ML sensing scheme. In addition, multi-V t transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharging speed by 2× when compared with the standard-V t devices at 1.2 V, 80°C. A test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 1.2 V/500 MHz. Index Terms-CAM, match-line, small match line swing, variation tolerant design.

ZnO precipitation experiments were carried out in a Trizma (tris(hydroxymethyl)aminomethane)-buffered aqueous solution at 37 °C and in the presence of three ZnO-binding 12-mer peptide pairs, which have nearly the same isoelectric point (pI). With this new approach, the influence of peptide sequences on ZnO mineralization under moderate conditions was investigated. Previous work was focused on electrostatic interactions between inorganic-binding peptides and inorganic surfaces. The precipitates were characterized by X-ray diffractometry (XRD), scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). Furthermore, the peptide binding to crystallographic planes of ZnO crystals was modeled by molecular dynamics (MD) simulation in explicit water. The binding free energies of all ZnO-binding peptides were calculated. The combined experimental and modeled results demonstrated a direct correlation between the binding strength of the peptide and the morphology of the ZnO particle, due to differences in their specific binding strength towards polar ZnO (001) and nonpolar (100) surfaces. As a consequence, the ZnO-binding peptides inhibited the growth of ZnO crystals by selective adsorption on the polar or nonpolar ZnO surfaces. This was demonstrated by comparison with a precipitation experiment under peptide-free conditions.

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