A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration

Claus, Christopher; Muller, F.; Zeppenfeld, Johannes; Stechele, Walter

doi:10.1109/ipdps.2007.370362

Cited by 60 publications

(36 citation statements)

References 8 publications

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“…In Figure 19 we present the global structure of our reconfigurable architecture that was implemented on the Xilinx Virtex-II Pro XC2VP30 FPGA on a XUP Board 7 . This particular type of structure is popular in the domain related to dynamic reconfigurable FPGAs, and various variants have been built from this classical structure, such as presented in (Claus et al 2007, Tumeo et al 2007). The choice of selecting the classical structure was 1) to compare our system with other existing partial dynamic reconfiguration based systems in literature, and 2) to provide the basic template for a model driven dynamically reconfigurable system that can be optimized by the domain experts, in order to generate their customized versions.…”

Section: Implementing a Partial Dynamically Reconfigurable Decmmentioning

confidence: 99%

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

Quadri

Gamatié

et al. 2010

IJES

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Abstract:As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools for handling SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach for addressing system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC co-design framework: Gaspard2. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented works are based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. Our contributions thus relate to presenting a complete design flow to move from high level MARTE models to automatic code generation, for implementation of dynamically reconfigurable SoCs.

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Section: Implementing a Partial Dynamically Reconfigurable Decmmentioning

confidence: 99%

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

Quadri

Gamatié

et al. 2010

IJES

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“…To reconfigure an entire FPGA device, even megabytes need to be transferred. The reconfiguration bandwidth can be as slow as a few MB/s (depending on the performance of the memory that stores the reconfiguration data) or up to more than 100 MB/s [CMZS07]. The reconfiguration time is typically in the range of milliseconds.…”

Section: Run-time Reconfigurable/dynamically Reconfigurablementioning

confidence: 99%

RISPP: A run-time adaptive reconfigurable embedded processor

Bauer

Shafique

Henkel

2009

2009 International Conference on Field Programmable Logic and Applications

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Hiermit erkläre ich an Eides statt, dass ich die von mir vorgelegte Arbeit selbständig verfasst habe, dass ich die verwendeten Quellen, Internet-Quellen und Hilfsmittel vollständig angegeben habe und dass ich die Stellen der Arbeit -einschließlich Tabellen, Karten und Abbildungen -die anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe. ____________________________________ L a r s B a u e r i AcknowledgementsI want to thank my advisor Prof. Jörg Henkel for the inspirations, discussions, and opportunities he provided and shared with me. He managed to guide and to challenge me while giving me all freedom to follow my ideas and interests. Working with him was a nice experience and it definitely had a strong influence on my independent approach to work.I also want to thank all colleagues from the Chair for Embedded Systems for the nice discussions and the good time. In the last two month before submitting my thesis, especially Thomas Ebi and Sebastian Kobbe provided consistent support by helping me managing the daily workload and by sharing their coffee machines, which I cannot appreciate enough. Additionally, it is especially due to the secretaries and technicians that we can research in a good working environment and I explicitly want to acknowledge their work during all the time.Special thanks go to my colleague and room mate Muhammad Shafique. Without him, the work would not have been what it became. The technical discussions on application-and architecture-aspects improved the quality of this work more than once. I also want to thank the Master students that I supervised in the scope of this thesis.It was a nice experience to collaborate with colleagues from the groups (in alphabetical order) of Prof. AbstractReconfigurable embedded processors are a special class of processors comprising an extended instruction set that is implemented using a reconfigurable fabric. The instruction-set extension is typically application specific, but it is not required to finalize it when designing the processor. The reconfigurable fabric (e.g. a field-programmable gate array (FPGA)) allows that the accelerators that are used to implement the instruction-set extension may be reconfigured during run time without affecting the functionality of the working processor. Therefore, the accelerators -and thus the instruction-set extension -may be adapted according to the requirements of a running application.State-of-the-art reconfigurable processors require that the application programmer (or compiler) determines during compile time 'which' reconfigurations shall be performed and 'when' they shall be performed, i.e. which accelerators shall be loaded to a particular part of the reconfigurable fabric at a certain time. The problem is that it is typically not known during compile time which applications execute at the same time (i.e. in a multi-tasking environment), demanding the reconfigurable fabric. Additionally, it is not necessa...

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“…Traditionally, access to the ICAP is made possible by using the OPBHWICAP peripheral attached to the On-Chip Peripheral Bus (OPB, see [2]) or by using a Xilinx Intellectual Property Interface (IPIF) peripheral attached to the Processor Local Bus (PLB, see [1]), with the operations of the ICAP controlled by software running on a processor core on the FPGA. However, the use of the OPB and PLB can take up relatively large amounts of resources; the need to integrate several components makes usage relatively complex; and the developed ICAP peripherals, such as the OPBHWICAP, were designed to be used with particular bus systems in each case.…”

Section: Introductionmentioning

confidence: 99%

“…al. [1] both investigated feasible platforms for reconfiguration using the ICAP with OPB-based and PLB-based systems respectively. Cuoccio et.…”

Section: Introductionmentioning

confidence: 99%

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ICAP-I: A reusable interface for the internal reconfiguration of Xilinx FPGAs

Lai

Diessel

2009

2009 International Conference on Field-Programmable Technology

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Abstract-Application circuits configured on Xilinx Virtex series FPGAs are able to reconfigure the FPGA at run time using the on-chip ICAP. Traditional methods of accessing the ICAP using OPB-based and PLB-based schemes are unnecessarily complex and rarely reused. In this study, a new interface for accessing the ICAP is introduced. The interface is easy to use, it can readily be integrated to different systems, it is customizable, and it is reusable. A demonstration is crafted to show the use of the new interface. Performance results for the new interface and two existing OPB-based and PLB-based methods are compared.

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A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration

Cited by 60 publications

References 8 publications

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

RISPP: A run-time adaptive reconfigurable embedded processor

ICAP-I: A reusable interface for the internal reconfiguration of Xilinx FPGAs

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