The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconf iguration, also known as dynamic partial reconf iguration (DPR). Taking this concept one step further, partial dynamic self-reconf iguration becomes possible through the Internal Conf iguration Access Port (ICAP). In this paper a framework for lowering reconf iguration times using the combitgen tool [2] to reduce the overhead found within bitstreams, along with a completely new, very simple and area eff icient ICAP controller that is connected directly to the Processor Local Bus (PLB) and is equipped with Direct Memory
In this paper, we defined a generic architecture for the extraction phase of a multi layer neural network algorithm to be implemented on a Virtex-4 FPGA. This architecture can be applied to any multi layer neural network composed of a given number of layers and a given number of neurons in each layer. In addition this architecture enhances the density of the FPGA by supporting the two concepts of time multiplexing and partial dynamic reconfiguration.Several networks with different sizes were implemented based on this generic architecture. Based on those implementations, we'll analyse the performances of a virtex-4 via a multi layer neural network by analyzing the variation of the minimum period and the number ofoccupied resources.This work was made in collaboration with the NodBox company (thierry.fargas@,&nodbox. biz) and Xilinx company (ean-louis. brelet@,xilinx. com).
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