A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation

Abstract

A new efficient type I architecture for motion estimation in video sequences based on the Full-Search Block-Matching (FSBM) algorithm is proposed in this paper. This architecture presents minimum latency, maximum throughput and full utilization of the hardware resources, combining both pipelining and parallel processing techniques. The implementation of an array processor for motion estimation in a single-chip using 0.25 Ilm CMOS technology is presented. Experimental results show that this processor is able to estimate motion vectors in 4CIF video sequences at a rate of 16 frames/so

Hardware Implementation of Block-based Motion Estimation for Real Time Applications

“…6, 7, 8, 9 and 10. The reconstructed images for best case and worst case MSE values for different sequences are shown in Figs. 11,12,13,14,15,16,17,18,19,20 …”

“…Other architectures [3,4] used 1D or 2D arrays derived from the dependence graphs of the full-search block-matching algorithm. In [15], a new architecture was presented to improve the bandwidth utilization, by reducing the amount of memory used to store the search area data. All the designs discussed above perform parallel processing on serial inputs, with multiple processing elements.…”

A spatial computing architecture for implementing computational circuits

“…To the study the architecture, a motion estimation (ME) algorithm was implemented based on an ASIC ME circuit [6]. Motion estimation is computationally intensive and highly parallelizable, yet requires a distributed control and communication network, so it is a good candidate for a computational circuit.…”