An Efficient VLSI Implementation for MC Interpolation of AVS Standard

A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264

“…2x and 4x implementations can support up to 30fps and 60fps for 1920x1080 video (See TABLE II). TABLE II also shows a comparison between our design and the previous ones in [6] and [7]. The number of adders and registers for buffering reference samples are compared, which may reflect the majority of hardware cost.…”

“…As illustrated in Figure 8, cfir is composed of an improved adder tree and a MUX for mode selection. In H.264 mode, all inputs of cfir (A to F) are active and P = A -5B + 20C + 20D -5E + F. In AVS mode, only 4 inputs are active (except for A and F) and P = 5C + 5D -B -E. This structure uses 7 adders, less than the sum of adders used in dedicated realizations for H.264 (6 adders) [5] and AVS (4 adders) [6].…”

An AVS/H.264 dual mode video decoder targeted at high definition video applications

“…However, the Motion Compensation (MC) is still a processing bottleneck in AVS video decoding. In the literature, there have been some researches proposed the VLSI implementation for MC interpolation in AVS [10][11]. But there are still problems in the designs [10][11] about how to effectively reduce the memory bandwidth for doing MC.…”

“…In the literature, there have been some researches proposed the VLSI implementation for MC interpolation in AVS [10][11]. But there are still problems in the designs [10][11] about how to effectively reduce the memory bandwidth for doing MC. Besides, there is high data overlapping in the neighboring reconstructed pixels among intra prediction, inter prediction, and compensation in the both H.264 and AVS.…”

Platform-independent MB-based AVS video standard implementation

“…Generally, there are two categories of video decoder implementations: one is the software-based decoder implementations for embedded video codec or applications on PC platform; the other is the hardware-based decoder implementations for chip design in consumer electronic devices. Most of the literatures about AVS decoder implementations focus on the second category [4][5][6][7][8][9][10][11]. Some of them propose the hardware decoder architecture for AVS video decoder implemented in a chip [4,5]; some of which just emphasize the implementation method for a specific coding tool, like variable length code (VLC) architecture for very-large-scale integration (VLSI) [6], the memory optimization for the VLC tables [7] by the data compression storage method, motion vector predictor architecture [8] for both AVS and MPEG-2, and VLSI implementation architectures for motion compensation (MC) [9][10][11].…”