A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264

Zhou, Dajiang; Liu, Peilin

doi:10.1109/iscas.2007.377858

Cited by 17 publications

(10 citation statements)

References 5 publications

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“…Some high-throughput interpolators have been proposed for H.264/AVC in literatures [5][6][7][8][9][10]. Usually, they are embedded in the fractional motion estimation pipeline stage that follows the integer-pel motion estimation.…”

Section: Introductionmentioning

confidence: 99%

An efficient interpolation filter VLSI architecture for HEVC standard

Zhou

Lian

et al. 2015

EURASIP J. Adv. Signal Process.

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The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

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Section: Introductionmentioning

confidence: 99%

An efficient interpolation filter VLSI architecture for HEVC standard

Zhou

Lian

et al. 2015

EURASIP J. Adv. Signal Process.

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“…The proposed method and implementation achieves over 217 fps for HD 720p and up to 95.9 fps when using the full HD 1080p streams. This is over 50% more than a maximum of 60 fps for HD frames obtained in [7]. For smaller image formats, the framerate is considerably higher: between 12623 fps for QCIF and 2502 fps for CIF format.…”

Section: Methods Results and Comparison To Existing Workmentioning

confidence: 83%

Novel data storage for H.264 motion compensation: system architecture and hardware implementation

Matei

Praet

Bauwelinck

et al. 2011

J Image Video Proc.

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Quarter-pel (q-pel) motion compensation (MC) is one of the features of H.264/AVC that aids in attaining a much better compression factor than what was possible in preceding standards. The better performance however also brings higher requirements for computational complexity and memory access. This article describes a novel data storage and the associated addressing scheme, together with the system architecture and FPGA implementation of H.264 q-pel MC. The proposed architecture is not only suitable for any H.264 standard block size, but also for streams with different image sizes and frame rates. The hardware implementation of a stand alone H.264 q-pel MC on FPGA has shown speeds between 95.9 fps for HD1080p frames, 229 fps for HD 720p and between 2502 and 12623 fps for CIF and QCIF formats.

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“…Sub-pixel interpolation is one of the most computationally intensive parts of HEVC. Compared with the 6-tap filter used in H.264/AVC [4], the 7-tap and 8-tap filters cost more area in hardware implementation and occupy 37%~50% of the total complexity for its DRAM access and filtering. Therefore it is necessary to design dedicated hardware architecture for interpolation filter to realize the realtime processing for high resolutions video.…”

Section: Introductionmentioning

confidence: 99%

An efficient interpolation filter VLSI architecture for HEVC

Zhou

Lian

2015

2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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Firstly, an implementation-friendly interpolation filter algorithm is proposed in this paper. It can save 19.6% processing time on average with negligible coding quality degradation. Then based on the proposed algorithm, an optimized interpolation filter VLSI architecture, composed of the reused data path of interpolation, efficient memory organization and the pipeline interpolation filter engine is presented to reduce the implement hardware area. The resulting design can achieve 240 MHz with only 37.2K gate count and support real-time interpolation filter operation of 3840×2160@47fps video application by using 90nm CMOS technology.

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A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264

Cited by 17 publications

References 5 publications

An efficient interpolation filter VLSI architecture for HEVC standard

An efficient interpolation filter VLSI architecture for HEVC standard

Novel data storage for H.264 motion compensation: system architecture and hardware implementation

An efficient interpolation filter VLSI architecture for HEVC

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