A modular 0.13 μm bulk CMOS technology for high performance and low power applications

Han, Liang; Biesemans, S.; Heidenreich, J.; Houlihan, K.; Lin, Choppy; McGahay, V.; Schiml, T.; Schmidt, Andrei; Schroeder, Uwe; Stetter, M.; Wann, C.; Warner, D.K.; Mahnkopf, R.; Chen, B.

doi:10.1109/vlsit.2000.852749

Cited by 16 publications

(8 citation statements)

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“…Thus, as the lithography pushes forward, the device designer and the product designer must devise new strategies to cope with the interference of passive power, which pushes for higher V T (and thus higher V DD ) versus active power, which demands lower V DD and thus lower V T . This results in fragmentation of device design points that address these conflicting needs in the foundry-CMOS business [5,6], where multiple values of T OX , V T , L GATE , and V DD are offered within a lithography generation (see Table 1). This approach allows the product designer flexibility to choose the best device match for active and passive power vs. performance.…”

Section: The Gordian Knot Of Cmos Scalingmentioning

confidence: 99%

Maintaining the benefits of CMOS scaling when scaling bogs down

Nowak

2002

IBM J. Res. & Dev.

187

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A survey of industry trends from the last two decades of scaling for CMOS logic is examined in an attempt to extrapolate practical directions for CMOS technology as lithography progresses toward the point at which CMOS is limited by the size of the silicon atom itself. Some possible directions for various specialized applications in CMOS logic are explored, and it is further conjectured that double-gate MOSFETs will prove to be the dominant device architecture for this last era of CMOS scaling.

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Section: The Gordian Knot Of Cmos Scalingmentioning

confidence: 99%

Maintaining the benefits of CMOS scaling when scaling bogs down

Nowak

2002

IBM J. Res. & Dev.

187

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“…Such a thin gate-oxide of only ~2nm in a 130nm CMOS technology has been reported to result in a substantial fraction of the overall leakage current in the chip due to its gate leakage current [7]. To reduce the gate leakage current, the high-k metal gate technology is applied in 45-nm generation and beyond [8], [9].…”

Section: * This Work Was Supported By Ministry Of Economic Affairs Tmentioning

confidence: 99%

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Ker

Wang

2009

2009 IEEE Custom Integrated Circuits Conference

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Electrostatic discharge (ESD) protection for mixedvoltage I/O interfaces has been one of the major challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. Moreover, the gate leakage current across thin gateoxide devices has serious degradation on circuit performance while circuits implementing in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O buffers should meet the gate-oxide reliability constraints and be designed with consideration of gate leakage current. This paper presents the effective ESD protection scheme with circuit solutions to protect the mixed-voltage I/O buffers in nanoscale CMOS processes against ESD stresses. The proposed ESD protection scheme and the specific ESD clamp circuits with low standby leakage current have been successfully verified in nanoscale CMOS processes. Effective on-chip ESD protection scheme should be early planed and started in the beginning phase of chip design in order to achieve good enough ESD robustness for IC products.

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“…To ensure the best possible performance in bulk silicon technology at competitive cost, the Blue Gene/L chip was designed and fabricated in the IBM standard 0.13-lm bulk CMOS offering [21]. The basic device characteristics The technology specifications for off current are approximately 0.3 nA/lm for both devices, with maximum off currents of 2 nA/lm and 1 nA/lm for n-FET and p-FET at a 6r short gate length of 70 nm.…”

Section: Device Considerationsmentioning

confidence: 99%

Embedded DRAM: Technology platform for the Blue Gene/L chip

et al. 2005

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The Blue Genet/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPCt cores, highperformance static random access memory (SRAM), DRAM, and several other logic design blocks on a single-platform technology. The IBM embedded DRAM platform allows this seamless integration without compromising performance, reliability, or yield. We discuss the process architecture, the key parameters of the logic components used in the processor cores and other logic design blocks, the SRAM features used in the L2 cache, and the embedded DRAM that forms the L3 cache. We also discuss the evolution of embedded DRAM technology into a higherperformance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance.

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A modular 0.13 μm bulk CMOS technology for high performance and low power applications

Cited by 16 publications

References 1 publication

Maintaining the benefits of CMOS scaling when scaling bogs down

Maintaining the benefits of CMOS scaling when scaling bogs down

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Embedded DRAM: Technology platform for the Blue Gene/L chip

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