A modified histogram approach for accurate self-characterization of analog-to-digital converters

Parthasarathy, K.L.; Jin, Le; Chen, Degang; Geiger, R.L.

doi:10.1109/iscas.2002.1011003

Cited by 16 publications

(9 citation statements)

References 5 publications

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“…Built-in self-test (BIST) structures for analog and mixed-signal circuits are widely recognized as a potential testing alternative for not only reducing costs associated with using production testers but also providing a capability to test deeply embedded systems on a chip (SOCs). BIST approaches can also provide value added and performance enhancement if incorporated with self-calibration functionality [3]. There have been numerous attempts to provide BIST solutions for ADCs, and most approaches in the literature [4]- [11] have concentrated on duplicating the operation or performance of a standard tester on-chip.…”

Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

“…A new approach to accurately testing an ADC in a production or BIST environment with dramatically reduced accuracy requirements on the test signal generator was recently introduced [3], [12]- [14]. With this approach, signal-processing techniques are used to accurately extract performance characteristics of the DUT that are embedded in output test data generated with low-accuracy signal generators.…”

Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

“…With this approach, signal-processing techniques are used to accurately extract performance characteristics of the DUT that are embedded in output test data generated with low-accuracy signal generators. In [3], a test algorithm was developed that takes advantage of inherent redundancy in two nonlinear input signals to accurately test ADCs. In [12], a test algorithm incorporated information about the spatial frequency separation of the nonlinear input spectrum from that of the DUT to characterize an ADC to accuracies that far exceed the linearity of the stimulus.…”

Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

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A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Olleta

Jiang

Chen

et al. 2006

IEEE Trans. Instrum. Meas.

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Abstract-Dynamic element matching (DEM) is capable of providing good average linearity performance in matching critical circuits in the presence of major component mismatch, but the approach has received minimal industrial adoption outside of Σ−∆ structures because of challenges associated with implementation of a required randomizer and because of the time-local nonstationarity. This paper presents a DEM approach to analog-to-digital converter (ADC) testing in which low-precision DEM digitalto-analog converters (DACs) are used to generate stimulus signals for ADCs under test. It is shown that in a testing environment, this approach provides very high precision test results, and timelocal nonstationarity is of no concern. In addition to traditional random DEM techniques, a deterministic DEM (DDEM) strategy that eliminates the need for a randomizer is introduced. The performance of the DDEM method is established mathematically and validated with detailed simulation results. Furthermore, the DDEM method requires far fewer samples to achieve the same level of average linearity than the random DEM approach. It is demonstrated that both the random DEM and DDEM methods can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique of using imprecise excitations and DEM to test much more accurate ADCs offers potential for use in both production test and built-in self-test environments where high linearity test sources are difficult to implement.Index Terms-Analog-to-digital converter (ADC) testing, built-in self-test (BIST), dynamic element matching (DEM), integral nonlinearity (INL) testing.

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Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

Section: A Deterministic Dynamic Element Matching Approach For Testinmentioning

confidence: 99%

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A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Olleta

Jiang

Chen

et al. 2006

IEEE Trans. Instrum. Meas.

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“…Furthermore, such nonlinear sources can be placed on the device interface board (DIB) to reduce requirements and cost of the ATE or even incorporated on chip with a small die area to facilitate use in a design for test (DFT) or a built-in self-test (BIST) environment. Recent research using the concept of using nonlinear excitations for ADC testing can be found in [8], [9], [11]- [13], and [15]- [17]. As a proof of concept, two different approaches were discussed in the authors' previous work [8].…”

Section: Introductionmentioning

confidence: 99%

“…Recent research using the concept of using nonlinear excitations for ADC testing can be found in [8], [9], [11]- [13], and [15]- [17]. As a proof of concept, two different approaches were discussed in the authors' previous work [8]. One of these approaches was sensitive to device noise, making applications to precision ADCs difficult.…”

Section: Introductionmentioning

confidence: 99%

Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal

Jin

Parthasarathy

Kuyel

et al. 2005

IEEE Trans. Instrum. Meas.

115

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Abstract-Linearity testing of analog-to-digital converters (ADCs) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. This paper introduces the stimulus error identification and removal (SEIR) method for accurately testing ADC linearity using signal generators that may be significantly less linear than the device under test. In the SEIR approach, two imprecise nonlinear but functionally related excitations are applied to the ADC input to obtain two sets of ADC output data. The SEIR algorithm then uses the redundant information from the two sets of data to accurately identify the nonlinearity errors in the stimuli. The algorithm then removes the stimulus error from the ADC output data, allowing the ADC nonlinearity to be accurately measured. For a high resolution ADC, the total computation time of the SEIR algorithm is significantly less than the data acquisition time and therefore does not contribute to testing time. The new approach was experimentally validated on production test hardware with a commercial 16-bit successive approximation ADC. Integral nonlinearity test results that are well within the device specification of 2 least significant bits were obtained by using 7-bit linear input signals. This approach provides an enabling technology for cost-effective full-code testing of high precision ADCs in production test and for potential cost-effective chip-level implementation of a built-in self-test capability. Index Terms-Analog-to-digital converters (ADCs), integral nonlinearity (INL), linearity test, stimulus error identification and removal (SEIR).I. BACKGROUND T HE "histogram method" is a standard approach for quasi-static linearity testing of analog-to-digital converters (ADCs) [1]- [3]. However, during the past decade, linearity testing of ADCs has not received much research attention for several reasons. As long as best practices are followed, modern mixed-signal automated test equipment (ATE) can be used to make quasi-static linearity testing of ADCs a fairly straightforward production task for low-to-medium resolution ADCs [4]. High-precision delta-sigma ADCs are inherently sufficiently linear and do not require linearity testing. In the communications circuit area, high-speed pipelined ADCs are widely used and are usually production tested with high-frequency input signals [2], whereas quasi-static linearity testing is primarily used for debugging [5] or calibration [6]. Probably the biggest reason, however, can be attributed to the challenges associated with generating highly linear or spectrally pure test signals with no major technological breakthroughs occurring in this area in the past decade. Nevertheless, quasi-static linearity testing remains a test challenge for the production of certain classes of high performance ADCs, and the increasing downward production cost pressures are making the convenient use of expensive mixed-signal ATEs for testing low and medium resolution ADCs more difficult to justify. In this paper, emphasis ...

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ADC Non-Linearity Low-Cost Test Through a Simplified Double-Histogram Method

Jalón

Peralías

2010

J Electron Test

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A modified histogram approach for accurate self-characterization of analog-to-digital converters

Cited by 16 publications

References 5 publications

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal

ADC Non-Linearity Low-Cost Test Through a Simplified Double-Histogram Method

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