A mixed QoS SDRAM controller for FPGA-based high-end image processing

Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements

“…While high bandwidth can always be reached by a sufficiently long pipeline, latency is the key problem to reduce cache stalling. The Sonics IP is a complex, 7 stage architecture that has an inherently longer latency than the lean 2-stage architecture of similar clock frequency used in [8] and in this paper. Even though the authors of [18] highlight the importance of low latency access to avoid cache delays, they do not elaborate on the latency effect of the relatively long pipeline (In [18] only memory bandwidth and no latencies are published).…”

“…Figure 2 shows the block diagram. A more detailed description of the general architecture can be found in [8], this chapter focuses on the QoS implementation.…”

“…In [8] it was demonstrated that cache memory access times can be reduced significantly by giving cache accesses a higher priority than data path accesses.…”

“…To solve the access problem, previously [8] a 2 stage memory controller architecture with short access latency at high bandwidth utilization was proposed. In this paper we add a flow control mechanism that improves the real-time behavior allowing both high throughput real-time access and reduced cache stalling.…”

FPGA based efficient on-chip memory for image processing algorithms

“…An approach to increase data parallelism by using a multi-port cache is also implemented [15]. Another kind of memory-control interface in FPGA was proposed, in which parallel units have access to memory concurrently and achieve high bandwidth use [16]. Liu et al developed a technique to optimize memory access to scratchpad memories (SPMs) within loop nests in order to take advantage of data re-use [17].…”