2012
DOI: 10.1016/j.mejo.2012.05.001
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FPGA based efficient on-chip memory for image processing algorithms

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Cited by 5 publications
(2 citation statements)
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“…To optimze the performance of matrix multiplication, we employ the Z-Morton memory layout [8], which has been widely studied for the Cache oblivious algorithms on multithreaded CPUs [8,12] and image processing on FPGAs [4]. This memory layout increases both spatial and temporal locality of memory accesses of matrix multiplication and arithmetic operations [8].…”
Section: Matrix Multiplications and Memory Access Patternsmentioning
confidence: 99%
See 1 more Smart Citation
“…To optimze the performance of matrix multiplication, we employ the Z-Morton memory layout [8], which has been widely studied for the Cache oblivious algorithms on multithreaded CPUs [8,12] and image processing on FPGAs [4]. This memory layout increases both spatial and temporal locality of memory accesses of matrix multiplication and arithmetic operations [8].…”
Section: Matrix Multiplications and Memory Access Patternsmentioning
confidence: 99%
“…Z-Morton memory layout for both dense and sparse matrix[4,8]: (a) the translation from logical layout to physical layout, (b) the block-based compressed coordinates (BCOO, l × l block and l = 4 for our design) for pruned Winograd weights Divide and Conquer Matrix Multiplication1: function recursive-matmult(A, B, C) 2: n = A.rows 3:…”
mentioning
confidence: 99%