Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements

Abstract

Today high-end video and multimedia processing applications require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, SDRAM access optimization is a complex task, especially if multistream access with different QoS requirements is involved. In [8], a multi-stream DDR-SDRAM controller IP covering combinations of low latency requirements for processor cache access, hard realtime constraints for periodic video signals and hard real-time bursty accesses for video coprocessors was described. To handle these contradictory QoS requirements at high system performance, a combination of a 2-stage scheduling algorithm and static priorities were used. This paper describes an additional flow control which enhances the overall performance. Experiments with an FPGA based high-end video platform demonstrate the superiority of this architecture.

Application-specific workload shaping in multimedia-enabled personal mobile devices

“…Very recently, shaping has also been used in the particular context of designing multi-processor System-on-Chip (SoC) architectures. It has been shown that shaping on-chip traffic leads to reduced on-chip global buffer requirements and improves overall system performance and predictability [8,14]. Similar techniques have also been shown to be useful when applied to Networks-on-Chip (NoC) architectures, where again they result in improved worstcase response times and global buffer requirements (which in turn lead to reduced chip area and power consumption) [10].…”

Application-specific workload shaping in multimedia-enabled personal mobile devices

“…Very recently, shaping has also been used in the particular context of designing multiprocessor system-on-chip (SoC) architectures. It has been shown that shaping on-chip traffic leads to reduced on-chip global buffer requirements and improves overall system performance and predictability [Heithecker and Ernst 2005;Wandeler et al 2006]. Similar techniques have also been shown to be useful when applied to networks-on-chip (NoC) architectures, where again they result in improved worst-case response times and global buffer requirements (which, in turn, lead to reduced chip area and power consumption) [Manolache et al 2006].…”

“…Recently, shaping techniques have also attracted a lot of interest within the embedded systems domain [Cai and Lu 2005;Chiasserini and Rao 2001;Heithecker and Ernst 2005;Hu and Lu 2005;Poellabauer and Schwan 2004;Manolache et al 2006;Wandeler et al 2006]. Shaping has been used as a means for aggregating the workload of media-processing applications (e.g., video decoders) to create idle periods.…”

Identifying the sources of unpredictability in COTS-based multicore systems

“…The memory scheduler is often very dynamic and uses information about the memory state when scheduling to improve average bandwidth or reduce average latency. Optimizing bandwidth may involve preferring requests that target an open row in a bank [52], [46], [53], requests that fit with the current direction of the data path [54], [55], [56], or a combination of the two [57], [58], [59]. Example mechanisms that reduce average latencies is to prefer reads over writes [53], which is beneficial if reads are blocking while writes are posted, or let high-priority memory clients preempt lower priority clients [59].…”