A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

Aminzadeh, Hamed; Grasso, Alfio Dario; Palumbo, G.

doi:10.1109/access.2022.3147879

Cited by 10 publications

(3 citation statements)

References 65 publications

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“…1. the equivalent transconductance of all stages is much greater than their output conductance (g mi , g m2 , g mL 1/R i ); 2. the nulling resistor R C is much lower than R D and both are much smaller than the output resistors (R C R D R i ); 3. the compensation capacitors are much lower than the load capacitor and all are much larger than the parasitic capacitors (C L C C , C D C i ), the simplified amplifier transfer function, using the methodology described in [43], can be expressed by…”

Section: B Transfer Functionmentioning

confidence: 99%

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

2022

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This paper proposes an optimal design approach for three-stage amplifiers driving an ultra-wide range of load capacitor. To this end, efficient state-of-the-art solutions have been combined to develop a power-efficient frequency compensation solution. High-speed feedback pathways relying on Miller capacitors and current buffers are implemented within the amplifier scheme to push the non-dominant poles to high frequencies for small to medium load capacitors. A small resistor is also shared between the two pathways to improve the stability regardless of the load capacitor. A serial R-C branch is then added to extend the lower limit of load drive capability to small load capacitors. Gain margin is, for the first time in literature, analytically evaluated and included in the design phase. A prototype of the proposed amplifier is fabricated in 65-nm CMOS process with active area of 0.0017 mm 2 and 1.15 pF total compensation capacitance. It can drive the load capacitor range from 200 pF to 100 nF, while drawing a quiescent current of 7.4 µA from a 1.2-V input voltage supply. A unity-gain frequency of 1.67 MHz was measured with an average slew-rate of 1.31 V/µs, when the proposed amplifier is wired in unity-gain configuration to drive a 500-pF load capacitor.

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Section: B Transfer Functionmentioning

confidence: 99%

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

2022

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“…Generally, an exact symbolic analysis of OTAs is error-prone and time-consuming if it is done by hand, even for circuits with a small number of components [6]. In this regard, a computer-aided automatic symbolic resolution can be helpful by solving the circuit equations by mathematical solvers such as Cramer's rule [7].…”

Section: Introductionmentioning

confidence: 99%

Mathematical Root Simplification in Operational Amplifiers using an Ensemble Heuristic-Metaheuristic Algorithm

Behmanesh-Fard¹,

Yazdanjouei²,

Shokouhifar³

et al. 2023

Preprint

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Symbolic pole/zero analysis is an important step when designing an analog operational amplifier. Generally, a simplified symbolic analysis of analog circuits suffers from NP-hardness, i.e., an exponential growth of the number of symbolic terms of the transfer function with the circuit size. In this study, we present a mathematical model combined with a heuristic-metaheuristic solution method for the symbolic pole/zero simplification in operational transconductance amplifiers (OTA). At first, the circuit is symbolically solved and an improved root splitting method is applied to extract symbolic poles/zeroes from the exact expanded transfer function. Then, a hybrid algorithm based on heuristic information and a metaheuristic technique using simulated annealing is performed for the simplification of the derived symbolic pole/zero expressions. The developed method has been tested on three analog OTAs. The obtained results show the effectiveness of the proposed method to achieve accurate simplified symbolic pole/zero expressions with the least complexity.

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“…For instance, AC boosting compensation (ACBC) [2], active feedback frequency compensation (AFFC) [3], and differential feedback path (DFP) [7] have been introduced to enhance amplifier parameters compared with basic NMC and RNMC approaches. Commercial tendencies have led to even more complicated amplifiers to satisfy speed and power demands [18][19][20][21][22][23][24][25][26][27][28][29]. For instance, Ref.…”

Section: Introductionmentioning

confidence: 99%

Multi‐Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

et al. 2023

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Multistage amplifiers have become appropriate choices for high‐speed electronics and data conversion. Because of the large number of high‐impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500‐pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five‐stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 μW.

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A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

Cited by 10 publications

References 65 publications

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

Mathematical Root Simplification in Operational Amplifiers using an Ensemble Heuristic-Metaheuristic Algorithm

Multi‐Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

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