A methodology for propagating design tolerances to shape tolerances for use in manufacturing

2011 12th International Symposium on Quality Electronic Design

Nassif

et al. 2011

Self Cite

Design-manufacturing co-optimization has been earmarked as a key enabler of future technology scaling. Current manufacturing methods treat all transistors equally irrespective of their criticality in the design flow. In the presence of variations in the lithographic process, this leads to timing violations which reduces chip yield. In this paper, we develop a timing-driven process window optical proximity correction (TD-PWOPC) algorithm that tunes the mask generation for each transistor based on its electrical criticality in the design. Our method utilizes knowledge of timing information to generate delay bounds on each cell. It then develops a process variation aware OPC cost function for each cell to ensure that post-lithography delay lies within these bounds. This method uses a single image simulation coupled with simplified models for regular polysilicon layouts to predict though-process performance. We finally use a gradient-descent algorithm to minimize this cost function. Results show that the use of TD-PWOPC can reduce delay errors significantly compared to regular OPC at small runtime overheads of 4.5%.

Section: Introductionmentioning

confidence: 89%

Section: Iterations > Max_iterations ?mentioning

confidence: 98%

Section: Characterizationmentioning

confidence: 99%

Section: Iterations > Max_iterations ?mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Coupling timing objectives with optical proximity correction for improved timing yield

2011 12th International Symposium on Quality Electronic Design

Nassif

et al. 2011

Self Cite

Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects

IEEE Custom Integrated Circuits Conference 2010

Orshansky

2010

Self Cite

The current method of communicating process capabilities to the designer is in the form of ground rules. However, due to constraints on the complexity and number of rules, there may exist shapes that are design-rule clean but difficult to manufacture. This problem is exacerbated in local routes drawn on 1x metal (M1) which allows highly bidirectional shapes at tight spacing. On the other hand, local M1 routes have low parasitic resistance and capacitance as compared to device impedances. Hence there exists an opportunity to perturb these shapes to improve their manufacturability without significant performance impact. We propose to guide this perturbation by the amount of leeway available between the designed values and the ground ruleswhich we refer to as ground rule slack. In this paper, we utilize ground rule slack to generate tolerance bands for layout features. We further develop a tolerance-driven optical proximity correction (TD-OPC) algorithm which utilizes such tolerance bands to find a lithographically optimal mask solution for manufacturing. Our experiments on sample layouts shows that the use of this methodology helps reduce lithographic hotspots by 59% in comparison to process window optical proximity correction.

Shape slack: a design-manufacturing co-optimization methodology using tolerance information

J. Micro/Nanolith. MEMS MOEMS

Nassif

et al. 2013

Self Cite

The move to low-k1 lithography makes it increasingly difficult to print feature sizes that are a small fraction of the wavelength of light. With further delay in the delivery of extreme ultraviolet lithography, these difficulties will motivate the research community to explore increasingly broad solutions. We propose that there is significant research potential in studying the essential premise of the design/manufacturing handoff paradigm. Today this premise revolves around design rules that define what implementations are legal, and raw shapes, which define design intent, and are treated as a fixed requirement for lithography. In reality, layout features may vary within certain tolerances without violating any design constraints. The knowledge of such tolerances can help improve the manufacturability of layout features while still meeting design requirements. We propose a methodology to convert electrical slack in a design to shape slack or tolerances on individual layout shapes. We show how this can be done for two important implementation fabrics: (a) cell-library-based digital logic and (b) static random access memory. We further develop a tolerancedriven optical proximity correction algorithm that utilizes this shape slack information during mask preparation to ensure that all features prints within their shape slacks in presence of lithographic process variations. Experiments on 45 nm silicon on insulator cells using accurate process models show that this approach reduces postlithography delay errors by 50%, and layout hotspots by 47% compared to conventional methods. Banerjee et al.: Shape slack: a design-manufacturing co-optimization methodology. . . Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/15/2015 Terms of Use: http://spiedl.org/terms 157 Shayak Banerjee received his MS and PhD degrees in electrical engineering from The University of Texas at Austin in 2008 and 2010, respectively. He is currently with IBM Research at East Fishkill, New York where he is involved in design for manufacturability and co-optimization of design and lithography for submicron technologies. He has published over 15 papers in peer-reviewed conferences and holds several US patents. He received the IBM PhD Fellowship award for 2008-09 and 2009-10. He has also served on the technical program committee of ACISC and ISVLSI. Kanak B. Agarwal received his MS and PhD degrees in electrical engineering from University of Michigan, Ann Arbor in 2003 and 2004, respectively. He is currently working as a researcher at IBM Research Lab in Austin, Texas where he is involved in research and development of next generation computer systems, circuits and tools, and semiconductor technology for IBM Server and Microelectronics business. He has published over 80 papers in refereed conferences and journals and holds over 30 patents. He has served Banerjee et al.: Shape slack: a design-manufacturing co-optimization methodology. . . Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/15/2015 Terms of Use: http...