Shape slack: a design-manufacturing co-optimization methodology using tolerance information

Abstract

The move to low-k1 lithography makes it increasingly difficult to print feature sizes that are a small fraction of the wavelength of light. With further delay in the delivery of extreme ultraviolet lithography, these difficulties will motivate the research community to explore increasingly broad solutions. We propose that there is significant research potential in studying the essential premise of the design/manufacturing handoff paradigm. Today this premise revolves around design rules that define what implementations are legal, and raw shapes, which define design intent, and are treated as a fixed requirement for lithography. In reality, layout features may vary within certain tolerances without violating any design constraints. The knowledge of such tolerances can help improve the manufacturability of layout features while still meeting design requirements. We propose a methodology to convert electrical slack in a design to shape slack or tolerances on individual layout shapes. We show how this can be done for two important implementation fabrics: (a) cell-library-based digital logic and (b) static random access memory. We further develop a tolerancedriven optical proximity correction algorithm that utilizes this shape slack information during mask preparation to ensure that all features prints within their shape slacks in presence of lithographic process variations. Experiments on 45 nm silicon on insulator cells using accurate process models show that this approach reduces postlithography delay errors by 50%, and layout hotspots by 47% compared to conventional methods. Banerjee et al.: Shape slack: a design-manufacturing co-optimization methodology. . . Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/15/2015 Terms of Use: http://spiedl.org/terms 157 Shayak Banerjee received his MS and PhD degrees in electrical engineering from The University of Texas at Austin in 2008 and 2010, respectively. He is currently with IBM Research at East Fishkill, New York where he is involved in design for manufacturability and co-optimization of design and lithography for submicron technologies. He has published over 15 papers in peer-reviewed conferences and holds several US patents. He received the IBM PhD Fellowship award for 2008-09 and 2009-10. He has also served on the technical program committee of ACISC and ISVLSI. Kanak B. Agarwal received his MS and PhD degrees in electrical engineering from University of Michigan, Ann Arbor in 2003 and 2004, respectively. He is currently working as a researcher at IBM Research Lab in Austin, Texas where he is involved in research and development of next generation computer systems, circuits and tools, and semiconductor technology for IBM Server and Microelectronics business. He has published over 80 papers in refereed conferences and journals and holds over 30 patents. He has served Banerjee et al.: Shape slack: a design-manufacturing co-optimization methodology. . . Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/15/2015 Terms of Use: http...

Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

“…More recently, Banerjee, Agarwaal, Nassif and Orshansky also addressed the relation between lithography imperfections and design tolerances with the objective of improving the design-manufacturing interface and the design rules regarding manufacturability. 11,12 The precise lithography hotspot identification has also become a concern in both layout design and manufacturing. Several works 13,14 propose efficient algorithms that analyze the layout to identify critical shapes that produce excessive distortion.…”