Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

Abstract

Copyright noticeLithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations Sergio Gómez, Francesc Moll and Joan Mauricio Universitat Politècnica de Catalunya, Department of Electronic Engineering, Barcelona, Spain Abstract.A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the lithodegradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer.