Abstract:Design-manufacturing co-optimization has been earmarked as a key enabler of future technology scaling. Current manufacturing methods treat all transistors equally irrespective of their criticality in the design flow. In the presence of variations in the lithographic process, this leads to timing violations which reduces chip yield. In this paper, we develop a timing-driven process window optical proximity correction (TD-PWOPC) algorithm that tunes the mask generation for each transistor based on its electrical… Show more
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