A meta-stable leakage phenomenon in DRAM charge storage &amp;amp;#8212;Variable hold time

Yaney, D.S.; Lu, Chun-An; Kohler, R.A.; Kelly, MJ; Nelson, James T.

doi:10.1109/iedm.1987.191425

Cited by 54 publications

(50 citation statements)

References 3 publications

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“…• C increase in temperature [29,41,48,57,74]. In Figure 4a, we illustrate the impact of temperature dependence using two cells at two different temperatures: (i) typical temperature (55 • C, bottom row), and (ii) the worst-case temperature (85…”

Section: Temperature Dependence: Hot Cells Are Leakiermentioning

confidence: 99%

See 1 more Smart Citation

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Lee

Kim

Pekhimenko

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

187

328

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In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process variation, some outlier chips are much slower than others and cannot be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the highest supported (i.e., worst-case) DRAM temperature (85• C). In this paper, we show that typical DRAM chips operating at typical temperatures (e.g., 55• C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case.Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve performance. Using an FPGA-based testing platform, we first characterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55• C without sacrificing correctness. Based on this characterization, we propose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adaptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface.We evaluate AL-DRAM on a real system that allows us to reconfigure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors. We discuss and show why AL-DRAM does not compromise reliability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance.

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Section: Temperature Dependence: Hot Cells Are Leakiermentioning

confidence: 99%

“…DRAM cells are intrinsically leaky, and lose some of their charge even when they are not being accessed. At high temperatures, this leakage is accelerated exponentially [29,41,48,57,74], leaving a cell with less charge to drive the bitline when the cell is accessed -increasing the time it takes for the bitline to be charged.…”

Section: Introductionmentioning

confidence: 99%

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Lee

Kim

Pekhimenko

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

187

328

View full text Add to dashboard Cite

show abstract

“…Finally, it has been shown that to a good approximation the scaling of the RTN amplitude distribution can be modeled by an exponential function with average value given by (34): [6] with N dop the channel doping density, K a constant and δ slightly lower than 1. RTN in Dynamic Random Access Memories (DRAM) has already been reported in the late eighties (35,36), giving rise to the so-called variable retention time phenomenon. In this case, the trapping is associated with p-n junction leakage current and with traps in the silicon depletion region (37,38).…”

Section: Rtn and Memory Variabilitymentioning

confidence: 99%

(Invited) Random Telegraph Noise: From a Device Physicist's Dream to a Designer's Nightmare

Simoen¹,

Kaczer²,

Toledano-Luque³

et al. 2011

ECS Trans.

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An overview is given on Random Telegraph Noise (RTN) in MOS-based devices. First, the basic properties and physics are briefly outlined, emphasizing the stochastic nature of its main parameters: the capture and emission time constant, while its amplitude is fixed and specific for each trap. Different techniques exist to characterize RTN in MOS devices, either by time or frequency domain measurements. A distinction can also be made between dynamic equilibrium methods like noise spectroscopy or transient measurements, based on a Deep-Level Transient Spectroscopy approach. While single-device based RTN measurements are still of high value, for modern circuit applications, techniques are being developed allowing a fast assessment of RTN in a large number of transistors. The scaling of CMOS technologies to the 32 nm and below raises the issue of variability induced either by random dopant fluctuations or in general, by random charge fluctuations, both spatially and in time. As will be seen, the presence of traps responsible for RTN brings about an additional source of variability which may become dominant in future memories. Finally, it will be shown that RTN is not only a fundamental component of 1/f noise but the same oxide traps are also largely responsible for the Bias Temperature Instability (BTI) in scaled MOSFETs. This leads to a selfconsistent model for BTI and a stochastic approach towards the reliability prediction of deep submicron CMOS technologies.

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“…RTS (random telegraph signal)-like fluctuation was reported in data retention time of DRAM [1][2][3] and in junction leakage [4][5]. In this paper, in recess channel type DRAM cell transistor called Saddle-Fin (S-Fin) transistor [6] in Fig.…”

Section: Introductionmentioning

confidence: 94%

RTS-like fluctuation in Gate Induced Drain Leakage current of Saddle-Fin type DRAM cell transistor

Kim

Kim²,

Oh³

et al. 2009

2009 IEEE International Electron Devices Meeting (IEDM)

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RTS (random telegraph signal)-like fluctuation in GateInduced Drain Leakage (GIDL) current of Saddle-Fin (S-Fin) type DRAM cell transistor was investigated for the first time. Furthermore, two types of fluctuation which have apparently different τ high (average time duration of high leakage state) to τ low (average time duration of low leakage state) ratio were investigated, and it was found that the energy difference between bistable levels is similar to that of the junction leakage.

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A meta-stable leakage phenomenon in DRAM charge storage &#8212;Variable hold time

Cited by 54 publications

References 3 publications

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

(Invited) Random Telegraph Noise: From a Device Physicist's Dream to a Designer's Nightmare

RTS-like fluctuation in Gate Induced Drain Leakage current of Saddle-Fin type DRAM cell transistor

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