A low-power PLA for a signal processor

Linz, A.

doi:10.1109/4.68124

Cited by 6 publications

(3 citation statements)

References 3 publications

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“…4(a) and 4(b). The component power dissipations are also listed for Po = 150 mW, based on (1) and (3). As anticipated, the principal loss arises from the forward voltage drop across D1 and Q1.…”

Section: Hybrid Led Transmittermentioning

confidence: 99%

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A 155-Mb/s LED transmitter with integral power conditioning

Banwell¹

1993

IEEE Trans. Power Electron.

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There is a growing need to reduce the power consumption of the high-speed components in broadband telecommunications networks. This will require that power processing be treated simultaneously with signal processing in the development of new broadband products. The power consumption of fiberoptic transmitters, which can use either lasers or LED's, is considered to be relatively large. LED transmitters normally require considerably more operating power than lasers, which is often the deciding factor in the selection of a laser rather than an LED in short span 100-200 Mb/s fiber-optic links. The LED transmitter issue therefore represents a good opportunity for examining new strategies to improve power-hungry technologies. The overall performance of an LED transmitter can be enhanced by using the available supply voltage more efficiently through power conditioning. We demonstrate a prototype 155-Mb/s LED transmitter that achieves a threefold improvement in power efficiency.

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Section: Hybrid Led Transmittermentioning

confidence: 99%

“…One approach to meeting this challenge is to develop techniques that combine power processing with signal processing in the design process. Many digital integrated circuits already incorporate power reduction techniques and power-down operating modes [3]. However, many of the trade-offs in more complex systems are not understood [4].…”

Section: Introductionmentioning

confidence: 99%

A 155-Mb/s LED transmitter with integral power conditioning

Banwell¹

1993

IEEE Trans. Power Electron.

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“…The style is chosen depending on the timing strategy. For the purposes of high speed, low power (Wang and Jeng 1995) and small area, a dynamic CMOS NOR-NOR PLA is often used (Linz 1991, Blair 1992. Because of the PLA's structure, a new class of fault, known as cross point faults, often occurs.…”

Section: Introductionmentioning

confidence: 99%

Dynamic NOR-NOR PLA design with IDDQ testability

Wu¹,

Wang²,

Hwang³

et al. 1999

International Journal of Electronics

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Certain logic functions such as the control units of VLSI processors are di cult to be implemented by random logic. Since the programmable logic arrays (PLAs) can implement almost any Boolean function, they have become popular devices in the realization of both combinational and sequential circuits. Besides, due to high quality demand in the semiconductor market, the testing of PLAs becomes an important issue. Because the structure of the PLAs is basically arrays of transistors or gates, the traditional test generation algorithms for stuck-at faults are hard to be employed. Thus, many test-generation approaches and designs for PLA testability have been developed. The IDDQ test is one of the e ective techniques of detecting both bridge faults and open faults in CMOS integrated circuits. We present a testability con® guration of PLAs which will be transformed into inverters in the test mode so that the IDDQ testing with only two test vectors and low overhead circuitry for the detection of all the bridge faults and most of the open faults can be realized.

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VLSI CMOS Subsystem Design

Bellaouar

Elmasry

1995

Low-Power Digital VLSI Design

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A low-power PLA for a signal processor

Cited by 6 publications

References 3 publications

A 155-Mb/s LED transmitter with integral power conditioning

A 155-Mb/s LED transmitter with integral power conditioning

Dynamic NOR-NOR PLA design with IDDQ testability

VLSI CMOS Subsystem Design

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