Dynamic NOR-NOR PLA design with IDDQ testability

Abstract

Certain logic functions such as the control units of VLSI processors are di cult to be implemented by random logic. Since the programmable logic arrays (PLAs) can implement almost any Boolean function, they have become popular devices in the realization of both combinational and sequential circuits. Besides, due to high quality demand in the semiconductor market, the testing of PLAs becomes an important issue. Because the structure of the PLAs is basically arrays of transistors or gates, the traditional test generation algorithms for stuck-at faults are hard to be employed. Thus, many test-generation approaches and designs for PLA testability have been developed. The IDDQ test is one of the e ective techniques of detecting both bridge faults and open faults in CMOS integrated circuits. We present a testability con® guration of PLAs which will be transformed into inverters in the test mode so that the IDDQ testing with only two test vectors and low overhead circuitry for the detection of all the bridge faults and most of the open faults can be realized.

Design of an Inter‐plane Circuit for Clocked PLAs

“…Hopefully, the state transition of the inter-plane wire load can be fastened. Other considerations to improve the performance of PLAs include adding low overhead IDDQ testability [8,9]. Nevertheless, all of the mentioned improved circuits unavoidably introduces either the full swing charging time or discharging time.…”