Certain logic functions such as the control units of VLSI processors are di cult to be implemented by random logic. Since the programmable logic arrays (PLAs) can implement almost any Boolean function, they have become popular devices in the realization of both combinational and sequential circuits. Besides, due to high quality demand in the semiconductor market, the testing of PLAs becomes an important issue. Because the structure of the PLAs is basically arrays of transistors or gates, the traditional test generation algorithms for stuck-at faults are hard to be employed. Thus, many test-generation approaches and designs for PLA testability have been developed. The IDDQ test is one of the e ective techniques of detecting both bridge faults and open faults in CMOS integrated circuits. We present a testability con® guration of PLAs which will be transformed into inverters in the test mode so that the IDDQ testing with only two test vectors and low overhead circuitry for the detection of all the bridge faults and most of the open faults can be realized.
Certain logic functions such as the control units of VLSI processors are difficult to implement by random logic. Since the programmable logic arrays (PLA's) can implement almost any Boolean function, they have become popular devices in the realization of both combinational and sequential circuits. We present a low-power high-speed complementary-metal-oxide semiconductor (CMOS) circuit implementation of NOR-NOR PLA using a single-phased clock. Buffering static NAND gates are inserted between the NOR planes to erase the racing problem and shorten the duration of glitches such that the dynamic power is reduced in addition to the low static power dissipation, no ground switch, no charge sharing, and zero offset.
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