A low-power and high-speed dynamic PLA circuit configuration for single-clock CMOS

Wang, Chua-Chin; Wu, Cheng‐Li; Hwang, Rain-Ted; Kao, Chia-Hsiung

doi:10.1109/81.774233

Cited by 16 publications

(1 citation statement)

References 5 publications

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“…The design combined an improved speed performance over the conventional dynamic implementation for large single-clock driven designs, while reducing the static power dissipation associated with a pseudo-NMOS implementation. But it is hard to drive a large capacitance load; bcause the PMOS load transistor is constrained by the sizing ratio [8] .…”

Section: Mixed Style Plamentioning

confidence: 99%

A new approach to Programmable Logic Array for single-clock CMOS

Yin

Tong

Gao

2006

J. of Electron.(China)

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Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.

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Section: Mixed Style Plamentioning

confidence: 99%

A new approach to Programmable Logic Array for single-clock CMOS

Yin

Tong

Gao

2006

J. of Electron.(China)

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Reconfigurable magnetoelectronic circuits for threshold logic

Carter

Ferrera

2004

Circuit Theory & Apps

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SUMMARYMagnetoelectronic devices, which combine ferromagnetic materials with conventional silicon structures, o er the potential to add non-volatile storage to electronic systems, eliminating their vulnerability to data loss due to power supply interruptions. We present a set of circuits, based on the Hybrid Hall E ect device, that combine logic with non-volatile storage. These circuits can be conÿgured on a cycleby-cycle basis to compute di erent functions of their inputs, store their outputs indeÿnitely even in the absence of system power, and can be easily integrated into CMOS systems to provide non-volatile operation without requiring additional supply voltages or other global signals. They exploit the properties of the Hybrid Hall E ect device to e ciently implement threshold logic functions and thereby reduce the number of gates required to implement most Boolean expressions.In this paper, we describe our reconÿgurable magnetoelectronic circuits and the interfaces that make them compatible with CMOS systems. The results presented are based on data from fabricated experimental devices, and we discuss how they can be expected to improve as devices scale to nanometer dimensions. Finally, we consider how magnetoelectronic circuits might be integrated into system designs to deliver high performance while tolerating power supply interruptions.

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