A low latency generic accuracy configurable adder

Shafique, Muhammad; Ahmad, Waqas; Hafiz, Rehan; Henkel, Jörg

doi:10.1145/2744769.2744778

Cited by 276 publications

(114 citation statements)

References 14 publications

(30 reference statements)

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“…In the inaccurate sub-adder, the inputs between adjacent LUTs are shared to minimize the error in the corresponding sum bits, while the accurate sub-adder could make use of the fast carry logic embedded in an FPGA slice. However, the drawback with Reference [22] is that only ASIC-oriented approximate adders, such as References [15,[23][24][25][26], were considered for a FPGA implementation and comparison, and the native accurate FPGA adder was left out of the comparison, as pointed out in Reference [27]. Based on a Virtex-7 FPGA implementation using Vivado 2015.1, it was noted in Reference [27] that the 32-bit and 64-bit FAU of [22] report maximum frequencies of 328.19MHz and 281.06MHz respectively, whereas the native accurate 32-bit and 64-bit FPGA adders report significant increases in maximum frequencies by 116% and 85%.…”

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confidence: 99%

Hardware Optimized and Error Reduced Approximate Adder

Balasubramanian

Maskell

2019

Electronics

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This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)-and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% fewer look-up tables (LUTs) and 18.6% fewer registers while reducing the minimum clock period by 7.1% and reducing the power-delay product (PDP) by 14.7%, compared to the native accurate FPGA adder, and (ii) for 64-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 11% fewer LUTs and 9.3% fewer registers while reducing the minimum clock period by 8.3% and reducing the PDP by 9.3%, compared to the native accurate FPGA adder. Based on ASIC-style implementations, HOERAA is found to achieve the following reductions in design metrics compared to an optimum accurate carry-lookahead adder: (i) A 15.7% reduction in critical path delay, a 21.4% reduction in area, and a 35% reduction in PDP for 32-bit addition involving a 8-bit least significant inaccurate sub-adder, and (ii) a 15.3% reduction in critical path delay, a 10.7% reduction in area, and a 20% reduction in PDP for 64-bit addition involving a 8-bit least significant inaccurate sub-adder. Moreover, comparisons with other approximate adders show that HOERAA has a significantly reduced average error, mean average error, and root mean square error, while reporting near optimum design metrics.2 of 15 predominant on approximate logic circuits [12] and approximate arithmetic circuits such as adders and multipliers [13]. Here, the focus is on the design of an approximate adder.Many approximate adders in the existing literature are suited for an application specific integrated circuit (ASIC)-style implementation and only some are suitable for both ASIC-and field programmable gate array (FPGA)-based implementations. Hence, it is unlikely that many approximate adders in the literature, when implemented on an FPGA, would surpass a native accurate FPGA adder of similar size because an FPGA embeds accurate arithmetic units, such as adders and multipliers, which are highly optimized for speed and area.This paper proposes a new approximate adder that is suitable for FPGA-and ASIC-based implementations, and our focus is on a comparison with other approximate adders, which are also suited for FPGA-and ASIC-based implementations. The remainder of this paper is organized as follows. A survey of some popular existing literature on approximate adders is presented in Section 2. Following this, we present the proposed approximate adder (HOERAA) in Section 3. FPGA-based implementation results corresponding to accurate and approximate adders for 32-bit and 64-bit additi...

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confidence: 99%

Hardware Optimized and Error Reduced Approximate Adder

Balasubramanian

Maskell

2019

Electronics

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“…3. Notice that a similar model was also proposed in [17]. In the model, the number of bits is n. Assume the two addends of an n-bit adder are A = a n−1 .…”

Section: Block-based Approximate Addersmentioning

confidence: 99%

An Efficient Method for Calculating the Error Statistics of Block-Based Approximate Adders

et al. 2019

IEEE Trans. Comput.

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Adders are key building blocks of many error-tolerant applications. Leveraging the application-level error tolerance, a number of approximate adders were proposed recently. Many of them belong to the category of block-based approximate adders. For approximate circuits, besides normal metrics such as area and delay, another important metric is the error measurement. Given the popularity of block-based approximate adders, in this work, we propose an accurate and efficient method to obtain the error statistics of these adders. We first show how to calculate the error rates. Then, we demonstrate an approach to get the exact error distribution, which can be used to calculate other error characteristics, such as mean error distance and mean square error.

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“…2 correspond to circuits with different trade-offs between WCE in % and the power-delay product (PDP 2 ), which is a key non-functional circuit characteristic. These circuits were obtained using various existing approaches including: (M1) configurable circuits from the lpACLib library [17], (M2) the bit-significance-driven logic compression [15], (M3) the bit-width truncation [10], (M4) compositional techniques [11], and (M5) circuits from the EvoApproxLib library [13]. We can see that just the bit-width truncation can provide a quality of results comparable with ADAC (in terms of the PDP reduction for the given WCE), but for large target errors (20% WCE or more) only.…”

Section: Evaluation Related Work and Applicationsmentioning

confidence: 99%

ADAC: Automated Design of Approximate Circuits

Češka

Matyas

Mrázek

et al. 2018

Computer Aided Verification

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Abstract. Approximate circuits with relaxed requirements on functional correctness play an important role in the development of resourceefficient computer systems. Designing approximate circuits is a very complex and time-demanding process trying to find optimal trade-offs between the approximation error and resource savings. In this paper, we present ADAC-a novel framework for automated design of approximate arithmetic circuits. ADAC integrates in a unique way efficient simulation and formal methods for approximate equivalence checking into a search-based circuit optimisation. To make ADAC easily accessible, it is implemented as a module of the ABC tool: a state-of-the-art system for circuit synthesis and verification. Within several hours, ADAC is able to construct high-quality Pareto sets of complex circuits (including even 32-bit multipliers), providing useful trade-offs between the resource consumption and the error that is formally guaranteed. This demonstrates outstanding performance and scalability compared with other existing approaches.

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A low latency generic accuracy configurable adder

Cited by 276 publications

References 14 publications

Hardware Optimized and Error Reduced Approximate Adder

Hardware Optimized and Error Reduced Approximate Adder

An Efficient Method for Calculating the Error Statistics of Block-Based Approximate Adders

ADAC: Automated Design of Approximate Circuits

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