A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation

Yang, Huishan; Lee, L.K.; Co, R.S.

doi:10.1109/4.563681

Cited by 37 publications

(11 citation statements)

References 9 publications

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“…Since the power supply noise is recognized as a major source of PLL jitter [11], a simple three-stage ring oscillator with less sensitivity to power supply noise is implemented. The VCO utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and operation over a wide range of power supply voltage [12], as shown in Fig. 6.…”

Section: Pllmentioning

confidence: 99%

Low power clock recovery circuit for passive HF RFID tag

Dai

Zhang

et al. 2009

Analog Integr Circ Sig Process

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A low power clock recovery circuit for passive HF RFID tag is presented. The proposed clock recovery circuit, based on the architecture of Phase Locked Loop (PLL), is used to generate a stable system clock when communication occurs from interrogator to tag with 100% ASK modulation. An envelope detector is designed to detect the incident power from interrogator and control the operating state of the proposed clock recovery circuit. Loop bandwidth of PLL circuits is minimized to reduce the frequency deviation when operating in frequency maintaining state. Furthermore, an initialization circuit for loop filter is also used to speed up locking during initial system power-on-reset. Prototype chips have been fabricated in 0.35 lm 2P4M CMOS technology. A total current consumption of 3 lA has been achieved in the frequency maintaining state. Measurement results show that, when communication occurs from interrogator to tag with 100% ASK modulation, clock recovery circuit generates a stable and consecutive system clock and has an inevitable frequency derivation of 7.5% when operating in frequency maintaining state.

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Section: Pllmentioning

confidence: 99%

Low power clock recovery circuit for passive HF RFID tag

Dai

Zhang

et al. 2009

Analog Integr Circ Sig Process

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“…The PLL is a charge-pump PLL [9], [10] and is based on the following blocks, shown in Fig. 2: the three-state phase and frequency detector (PFD), the charge-pump (CP), the RC loopfilter, the voltage controlled oscillator (VCO), and the VCO output buffer (BUF).…”

Section: A Pllmentioning

confidence: 99%

A 0.13-/spl mu/m CMOS serializer for data and trigger optical links in particle physics experiments

Cervelli

Marchioro

Moreira

2004

IEEE Trans. Nucl. Sci.

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A 3.2-Gbit/s serializer prototype has been fabricated in a 0.13-m CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-line driver, internal self-testing features, and data pattern generation. The serial output stream is 8 B/10 B encoded for compatibility with commercial receivers. Radiation hardening layout techniques have been adopted, which guarantee radiation tolerant operation inside the innermost LHC detectors over more than 10 yr. This paper describes the circuit architecture and reports on the experimental results. Signal quality (jitter, noise floor, eye opening) and bit-error rate (BER) are measured at different transmission rates using laboratory instrumentation and dedicated test beds.

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“…These design goals have received a lot of attention [10]- [14]. To minimize the PLL output clock jitter, the loop bandwidth must be set where the unfiltered noise spectral density of the reference and input electronics equal the VCO noise spectral density [15].…”

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confidence: 99%

PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element

Pauls

Kalkur

2007

IEEE Trans. Ultrason., Ferroelect., Freq. Contr.

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Ferroelectric capacitors have steadily been integrated into semiconductor processes due to their potential as storage elements within memory devices. Polarization reversal within ferroelectric capacitors creates a high nonlinear dielectric constant along with a hysteresis profile. Due to these attributes, a phase-locked loop (PLL), when based on a ferroelectric capacitor, has the advantage of reduced cycle-to-cycle jitter. PLLs based on ferroelectric capacitors represent a new research area for reduction of oscillator jitter.

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A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation

Cited by 37 publications

References 9 publications

Low power clock recovery circuit for passive HF RFID tag

Low power clock recovery circuit for passive HF RFID tag

A 0.13-/spl mu/m CMOS serializer for data and trigger optical links in particle physics experiments

PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element

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