2009
DOI: 10.1007/s10470-008-9276-4
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Low power clock recovery circuit for passive HF RFID tag

Abstract: A low power clock recovery circuit for passive HF RFID tag is presented. The proposed clock recovery circuit, based on the architecture of Phase Locked Loop (PLL), is used to generate a stable system clock when communication occurs from interrogator to tag with 100% ASK modulation. An envelope detector is designed to detect the incident power from interrogator and control the operating state of the proposed clock recovery circuit. Loop bandwidth of PLL circuits is minimized to reduce the frequency deviation wh… Show more

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Cited by 7 publications
(3 citation statements)
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“…As low-cost tags do not possess an on-chip clock, a capacitor's discharge time [77] can be enough for a rough estimate of the round trip time (distance). Alternatively, a clock recovery circuit based on a phase-locked loop can be used, as shown in the prototype designed by Bo et al [7]. Independently of the approach followed, in our proposal a certain degree of inaccuracy (e i ) regarding distance (d i ) does not represent a major security risk.…”
Section: Distance-bounding Protocolsmentioning
confidence: 98%
“…As low-cost tags do not possess an on-chip clock, a capacitor's discharge time [77] can be enough for a rough estimate of the round trip time (distance). Alternatively, a clock recovery circuit based on a phase-locked loop can be used, as shown in the prototype designed by Bo et al [7]. Independently of the approach followed, in our proposal a certain degree of inaccuracy (e i ) regarding distance (d i ) does not represent a major security risk.…”
Section: Distance-bounding Protocolsmentioning
confidence: 98%
“…The difference between two clocks at any point in time is called clock skew and is due to both clock drift and the possibility that the clocks may have been set differently on different machines. It has been studied in [21,22,23] that the frequency deviation for NFC and RFID working at 13.56MHz is about 1% . This frequency deviation is inevitable and may also change in different devices, and be affected by environmental factors such as temperature and circuit ageing.…”
Section: Basic Schemementioning
confidence: 99%
“…However, the solutions OE2 4 only provide a discontinuous clock because of the "pause" generated by OOK modulation in the carrier. Although Reference [5] can provide the consecutive clock, low sensitivity to OOK signal leads to high frequency deviation, which increases the probability of error demodulation. In particular, under the mobile payment application, it tends to fail due to the weak OOK signal.…”
Section: Introductionmentioning
confidence: 99%