A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs

Perez, W. J. H.; Velasco, Josè M.; Ravotto, D.; Sánchez, Ernesto; Reorda, Matteo Sonza

doi:10.1109/iolts.2008.22

Cited by 20 publications

(4 citation statements)

References 12 publications

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“…• By resorting to the performance counters [10] existing in many processors and able to monitor the number of correctly/incorrectly executed predictions • By resorting to a timer able to measure the performance of the processor when executing a given piece of code, exploiting the fact that mispredictions imply longer execution time • By resorting to some debug feature provided by the processor [13] • By resorting to some ad-hoc module added to the system and able to monitor the bus activity [11].…”

Section: Test Of a 1-bit Bhtmentioning

confidence: 99%

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

Sanchez¹,

Reorda²,

Tonda³

2012

VLSI-SoC: Advanced Research for Systems on Chip

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Abstract. Branch Prediction Units (BPUs) are commonly used in pipelined processors, since they can significantly decrease the negative impact of branches in superscalar and RISC architectures. Traditional solutions, mainly based on scan, are often inadequate to effectively test these modules: in particular, scan does not represent a viable solution when Incoming Inspection or on-line test are considered. Functional test may stand as an effective solution in these situations, but requires effective algorithms to be available. In this paper we propose a functional approach targeting the test of BPUs based on the Branch History Table (BHT) architecture; the proposed approach is independent on the specific implementation of the BPU, and is thus widely applicable. Its effectiveness has been validated on a BPU resorting to an opensource computer architecture simulator and to an ad hoc developed HDL testbench. Experimental results show that the proposed method is able to thoroughly test the BPU, reaching complete static fault coverage with reasonable requirements in terms of test program size and execution time.

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Section: Test Of a 1-bit Bhtmentioning

confidence: 99%

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

Sanchez¹,

Reorda²,

Tonda³

2012

VLSI-SoC: Advanced Research for Systems on Chip

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“…This technique relies on an accurate timer to validate cache memory operations. Whenever an accurate timer is not available an alternative solution based on the use of an Infrastructure Intellectual Property core (I-IP) is proposed [28].…”

Section: Software-based Solutionsmentioning

confidence: 99%

Software-Based Self-Test of Set-Associative Cache Memories

Carlo

Prinetto

Savino

2011

IEEE Trans. Comput.

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Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software based self test programs for setassociative cache memories with LRU replacement. Among all the different cache blocks in a microprocessor, testing instruction caches represents a major challenge due to limitations in two areas: (i) test patterns which must be composed of valid instruction opcodes; and (ii) test result observability: the results can only be observed through of the results of executed instructions. For these reasons the proposed methodology will concentrate on the implementation of test programs for instruction caches. The main contribution of this work lies in the possibility of applying state-of-the-art memory test algorithms to embedded cache memories without introducing any hardware or performance overheads and guaranteeing the detection of typical faults arising in nanometer CMOS technologies.

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“…Some of the addressed units (e.g., the caches) include relatively large memories [6] : for this reason the test often addresses first the memory, and the proposed algorithms have been shown to test them well. In a second step, the surrounding logic is also addressed, and the proposed algorithms are possibly improved to test it as well [5].…”

mentioning

confidence: 99%

On the functional test of the BTB logic in pipelined and superscalar processors

Changdao

Graziano

Sánchez

et al. 2013

2013 14th Latin American Test Workshop - LATW

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Electronic systems are increasingly used for safety critical applications, where the effects of fa ults must be taken under control and hopefully avoided. For this purpose, test of manufactured devices is particularly important, both at the end of the production line and during the operational phase. This paper describes a method to test the logic implementing the Branch Prediction Unit in pipelined and superscalar processors when this fo llows the Branch Target Buffer (BTB) architecture; the proposed approach is fu nctional, i.e., it is based on fo rcing the processor to execute a suitably devised test program and observing the produced results. Experimental results are provided on the DLX processor, showing that the method can achieve a high value of stuck-at fault coverage while also testing the memory in the BTB.

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A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs

Cited by 20 publications

References 12 publications

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

Software-Based Self-Test of Set-Associative Cache Memories

On the functional test of the BTB logic in pipelined and superscalar processors

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