Software-Based Self-Test of Set-Associative Cache Memories

Abstract

Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software based self test programs for setassociative cache memories with LRU replacement. Among all the different cache blocks in a microprocessor, testing instruction caches represents a major challenge due to limitations in two areas: (i) test patterns which must be composed of valid instruction opcodes; and (ii) test result observability: the results can only be observed through of the results of executed instructions. For these reasons the proposed methodology will concentrate on the implementation of test programs for instruction caches. The main contribution of this work lies in the possibility of applying state-of-the-art memory test algorithms to embedded cache memories without introducing any hardware or performance overheads and guaranteeing the detection of typical faults arising in nanometer CMOS technologies.

MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches

“…α identifies the set in which the line must be written and t identifies the tag written in the directory array of cache. We will not discuss the complex addressing order translations presented in [11] since, in its current implementation, our generation tools deals with direct-mapped data cache memories whose cache lines are directly addressable. According to the internal cache organization, the test approaches for data and directory array are different.…”

“…Most of them propose different methodologies to adapt existing March tests [7] to cache memories, taking into account the functional and/or the RTL model [8], [9], [10], [11], [12], [13], [14], [15]. Differences in the proposed approaches mainly lay in the portion of the cache addressed by the test (e.g., [12], [13], [10], [11], [9] mainly target faults in the memory array of the cache, while [14] concentrates on its control logic). Some solutions, such as the one proposed by Sosnowski in [15], also propose the use of dedicated hardware (e.g., on-chip performance monitor) to increase the SBST test capability.…”

“…Among the test procedures presented in the literature, we will focus on the test procedure proposed in [11] which provides a detailed set of rules to translate generic March tests into a set of test programs for the data and the directory array of a generic memory. MarciaTesta exploits a library able to describe the ISA of the target microprocessor, thus automating the translation into the specific assembly code.…”

A Search Based Approach for Stress-Testing Integrated Circuits

“…There are established methodologies for targeted testing of cache memory at very low level as found in [24]. More standard techniques are outlined in the work published in [25]. Successful application of search based software testing methodology in the area of memory system validation can be seen in the work using genetic algorithms with memory consistency model (MCM) verification as per [26].…”

A Two Layered approach to perform Effective Page Replacement

“…Author defined the improvement over the CMOS technologies by reducing the memory faults over the cache. In year 2011, Mohamed Wassim Jmal [9] defined a work based on elliptical curve based algorithm to improve the aching process. The presented work is divided in stages.…”