“…Most of them propose different methodologies to adapt existing March tests [7] to cache memories, taking into account the functional and/or the RTL model [8], [9], [10], [11], [12], [13], [14], [15]. Differences in the proposed approaches mainly lay in the portion of the cache addressed by the test (e.g., [12], [13], [10], [11], [9] mainly target faults in the memory array of the cache, while [14] concentrates on its control logic). Some solutions, such as the one proposed by Sosnowski in [15], also propose the use of dedicated hardware (e.g., on-chip performance monitor) to increase the SBST test capability.…”