On the functional test of the BTB logic in pipelined and superscalar processors

Changdao, D.; Graziano, Mariagrazia; Sánchez, Ernesto; Reorda, M. Sonza; Zamboni, Maurizio; Zhifan, N.

doi:10.1109/latw.2013.6562677

Cited by 9 publications

(3 citation statements)

References 13 publications

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“…Software-Based Self-Test (SBST) [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] is an emerging paradigm in the test field. The major problem with SBST is usually the not sufficient test quality, measured by the single Stuck-at-Fault (SAF) coverage, let alone considering broader fault classes.…”

Section: Introductionmentioning

confidence: 99%

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On Test Generation for Microprocessors for Extended Class of Functional Faults

Oyeniran¹,

Ubar²,

Jenihhin³

et al. 2020

IFIP Advances in Information and Communication Technology

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We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testing microprocessors with RISC architecture to cover a large class of high-level functional faults. This is comparable to that used in memory testing which also covers a large class of structural faults such as stuck-at-faults(SAF), conditional SAF, multiple SAF and bridging faults. The approach is fully high-level, the model of the microprocessor is derived from the instruction set and architecture description, and no knowledge about gate-level implementation is needed. To keep the approach scalable, the microprocessor is partitioned into modules under test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, while for the control parts, a novel generic functional control fault model was developed. A novel method for measuring high-level fault coverage for the control parts of MUTs is proposed. The measure can be interpreted as the quality of covering the high-level functional faults, which are difficult to enumerate. We apply High-Level Decision Diagrams for formalization and optimization of high-level test generation for control parts of modules and for trading off different test characteristics, such as test length, test generation time and fault coverage. The test is well-structured and can be easily unrolled online during test execution. Experimental results demonstrate high SAF coverage, achieved for a part of a RISC processor with known implementation, whereas the test was generated without knowledge of implementation details.

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Section: Introductionmentioning

confidence: 99%

“…The method needs structural information. Later research has been concentrated on developing dedicated test approaches for specific processor parts like pipeline, branch prediction mechanism [11,21], caches [22,23].…”

Section: Introductionmentioning

confidence: 99%

On Test Generation for Microprocessors for Extended Class of Functional Faults

Oyeniran¹,

Ubar²,

Jenihhin³

et al. 2020

IFIP Advances in Information and Communication Technology

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“…Later research concentrates on test approaches for specific processor parts like pipeline, branch prediction mechanism [17][18] or caches [19][20]. In [21], a method is proposed, which can enhance SBST program in order to bring more coverage to pipeline logic and also memory addressing.…”

Section: Introductionmentioning

confidence: 99%

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Oyeniran¹,

Ubar

Jenihhin

et al. 2019

2019 IEEE European Test Symposium (ETS)

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Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementationindependent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudoexhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor. Keywords-RISC processors, high-level fault model, highlevel test generation, deterministic and pseudo-exhaustive tests, control and data path tests

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