A high-speed programmable CMOS interface system combining D/A conversion and FIR filtering

Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays

“…In a current-steering DAC without a dummy element, if all the current sources are numbered in the order they are switched on, the actual output current for digital code ( ) is thus given by (6) where is the offset current. It follows from 1 From (8) and (10), it is apparent that thermometer-decoded DAC's can achieve very low DNL .…”

“…The well-known row-column switching scheme is commonly used in a heuristic attempt to optimize the switching sequence [2]- [6]. In this scheme, the spatial gradient errors are averaged in two directions, as shown in Fig.…”

“…S EGMENTED architectures are widely used in high-conversion-rate and high-accuracy digital-to-analog converters (DAC's) [1]- [6]. Generally, the least significant bits (LSB's) steer a binary weighted array, while the most significant bits (MSB's) are thermometer decoded and steer a unary array.…”

“…Optimizing switching schemes can reduce the nonlinearity due to gradient errors. This potential has been seen in many current-steering DAC designs [1]- [6]. A switching scheme is actually a layout technique.…”

Design techniques for high-performance current-steering digital-to-analog converters

“…The well-known row-column switching scheme is commonly used in a heuristic attempt to optimize the switching sequence [5], [13], [14], [17], [47], [48]. In this scheme, the spatial gradient are averaged in two directions as shown in Figure 3.3 and the sequences for row and column selection are optimized independently.…”