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Wikner, J. Jacob; Tan, Nianxiong

doi:10.1023/a:1008340317904

Cited by 14 publications

(1 citation statement)

References 11 publications

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“…6 shows the Pelgrom plot [6] of linear V t mismatch results obtained before irradiation and after a total dose of 300 krad(SiO 2 ). The V t mismatch increases significantly after irradiation, with the average 'V t increasing by almost 3X, and some devices showing over 100 mV of 'V t with V t = 0.35 V. This greatly limits the performance of high precision analog circuits in space environments [7] and requires special care during circuit design to mitigate the damage. The increase of V t mismatch proves again that TID induces more local variability to device performance.…”

Section: Resultsmentioning

confidence: 99%

Including the effects of process-related variability on radiation response using a new test chip

Li¹,

Rezzak

Schrimpf

et al. 2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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Section: Resultsmentioning

confidence: 99%

Including the effects of process-related variability on radiation response using a new test chip

Li¹,

Rezzak

Schrimpf

et al. 2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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Modeling of Nyquist D/A Converters

Gustavsson¹,

Wikner²,

Tan³

CMOS Data Converter for Communications

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Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

Moon

Song

Shin³

et al. 2009

Analog Integr Circ Sig Process

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A compact and low power 12-bit 300 MS/s current steering CMOS D/A converter is presented. The architecture of the D/A converter is based on the current steering 6 ? 6 segmented type with a laminated current cell relocation technique. In order to improve the linearity and glitch noise, a high output impedance analog current cell is designed. Furthermore, for the purpose of reducing the chip area and power dissipation, a noble merged switching logic and a compact layout technique are proposed. To verify its performance, the chip was fabricated with 0.13 lm thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is 0.26 mm 2 (510 9 510 lm) with a power consumption of 100 mW. The measured INL and DNL are within ±3LSB and ±1LSB, respectively. The measured SFDR is about 70 dB, when the input frequency is 1 MHz at a clock frequency of 300 MHz.

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Untitled

Cited by 14 publications

References 11 publications

Including the effects of process-related variability on radiation response using a new test chip

Including the effects of process-related variability on radiation response using a new test chip

Modeling of Nyquist D/A Converters

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

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