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This paper proposes improved switched-capacitor (SC) interpolators using a novel sampling technique which eliminates the undesired distortion due to the sample-and-hold shaping effect at the lower input sampling rate. Such a sampling technique not only leads to a precise analog interpolation, as its digital counterpart does, but also allows to simplify the design procedures and resulting SC circuit implementations. Different circuit topologies with both finite-and infinite-impulse response characteristics are developed, respectively, for low-and high-selectivity filtering. Practical implementation issues are discussed with respect to capacitance ratio mismatches, as well as finite gain, bandwidth, and offset sensitivity effects of operational amplifiers. Besides detailed computer-based analyses, experimental results obtained from discrete component prototypes are also presented to demonstrate the proposed circuits.

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High-order Switched-Capacitor (SC) decimation circuits that achieve high input sampling ratios while minimizing the required operating speed of the amplifiers have been previously designed by cascading simpler first-and second-order decimation building blocks. This paper proposes alternative SC decimators combining low-sensitivity ladder structures together with highspeed polyphase networks. This is based on the transformation of the state equation of a conventional SC ladder filter clocked at the higher sampling frequency MFs into a multirate transfer function yielding a decimating structure with the same filtering characteristic and input sampling frequency of M F s but where the output sampling frequency is reduced to only FS to allow more time for the settling of the amplifiers. Two design examples of low-pass and band-pass SC decimators are given to illustrate the proposed design methodology. Detailed computer-based sensitivity analyses are carried-out to evaluate the performance of the resulting circuits.

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