This paper discusses switching schemes for gradient error compensation in unary (thermometer-decoded) arrays of digital-to-analog converters (DAC's). The absolute lower bound of integral nonlinearity (INL) by optimizing switching sequences is established and optimal switching sequences that meet the lower bound of INL are presented for linear error compensation in one-dimensional arrays. A rapidly converging algorithm is developed to obtain INL bounded switching sequences for any given type of gradient error compensation. Simulation results show that the new switching sequences substantially reduce the nonlinearity of DAC's due to gradient errors.

Abstract-Large-area current source arrays are widely used in current-steering digital-to-analog converters (DACs) to statistically maintain a required level of matching accuracy between the current sources. This not only results in large die size but also in significant degradation of dynamic range for high-frequency signals. To overcome technology barriers, relax requirements on the layout, and reduce DAC sensitivities to process, temperature, and aging, calibration is emerging as a viable solution for the next-generation high-performance DACs. In this paper, a new foreground calibration technique suitable for very-low-voltage environments is presented which effectively compensates for current source mismatch, and achieves high linearity with small die size and low power consumption. Settling and dynamic performance are also improved due to a dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit DAC prototype was implemented in a 0.13-m digital CMOS process. This is the first CMOS DAC reported that operates with a single 1.5-V power supply and achieves 14-bit linearity with less than 0.1 mm 2 of active area. At 100 MS/s, the spurious free dynamic range is 82 dB (62 dB) for signals of 0.9 MHz (42 MHz) and the power consumption is only 16.7 mW.

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