A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters

Furuta, Mamoru; Nishikawa, Yasuko; Inoue, Taiki; Kawahito, Shoji

doi:10.1109/jssc.2007.891655

Cited by 116 publications

(49 citation statements)

References 10 publications

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“…The differential circuit is a kind of transmission path that can suppress the noise both received from and generated to the surroundings [19]. The differential circuit generates two signals with the same absolute voltage and opposite phases on two balanced strip conductors.…”

Section: Suppression Of Crosstalk Using Differential Circuitmentioning

confidence: 99%

Uncertainty Visualization of Estimated Damage Using Kriging Model: Application to Time-Domain Reflectometry Sensing

2015

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We used a Kriging model to visualize the uncertainty of the estimated damage location from time domain reflectometry (TDR) measurements. The damage can be clearly detected on the transmission line through the application of a 2D microstrip line differential circuit for TDR. The reflection voltages between the observed points are interpolated, and the uncertainty is obtained by Kriging. We integrated the estimation and uncertainty contour maps into a single figure for easier understanding and statistical quantification. We used the measured TDR data to investigate three types of visualization models for damage inspection: hue-saturation-intensity color, crack existence probability, and expected improvement. All three methods quantitatively visualize the estimated crack configuration with uncertainty in a single figure. By operating these visualization models depending on the inspector's preferences, more appropriate crack estimation can be performed for wide-area fast scantype inspections such as TDR. In particular, the latter two models can be directly used as an evaluation index for secondary inspection.

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Section: Suppression Of Crosstalk Using Differential Circuitmentioning

confidence: 99%

Uncertainty Visualization of Estimated Damage Using Kriging Model: Application to Time-Domain Reflectometry Sensing

2015

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“…Table 1 summarizes the performance of this work and other related works used in CMOS imager sensors. Multiple-ramp Single-slope (MRSS) and 2-step Single-slope (2-step SS) ADCs feature in small channel area and low power [1,2]; SAR ADCs are highly power efficient [14]; cyclic ADCs perform high-resolution at fast conversion speed [15]. To assist a uniform comparison across different topologies, the throughput per unit time per unit chip area in bits (Mbit=ðs Â mm 2 Þ) for each reported ADC is measured.…”

Section: Performance Summary and Comparisonmentioning

confidence: 99%

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

Wang

Salthouse

2015

Microelectronics Journal

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a b s t r a c tThe Column-Parallel Overlapping-Subrange Successive-Approximation-Register Analog-to-Digital Converter (CPOSSAR ADC) uses a 5-bit split capacitor DAC twice to achieve 9-bit resolution. Its total capacitor area is only 3% of a 9-bit binary weighted DAC and the average switching power is only 12% of a conventional 9-bit DAC. The ADC can perform a 9-bit conversion by first digitizing the 4 most significant bits (MSB) in a coarse conversion stage and then digitizing the 5 least significant bits (LSB) in a fine conversion stage. The accuracy requirement of the DAC is reduced by using overlapping subranges. The proposed ADC achieved an SFDR of 73.6 dB and a SINAD of 55 dB in post-layout simulation, corresponding to an ENOB of 8.8 bits. The design was fabricated in a TSMC's 0.35 μm high-voltage process. The use of overlapping subranges reduced the DNL error from þ 5.14/ À1 LSB to þ 1.27/ À 0.92 LSB, and improved the INL error from þ 5.35/À 5.34 LSB to þ 3.17/À 3.18 LSB. At a sampling rate of 1.1 MS/s the ADC achieved 41.5 dB SFDR, 34.2 dB SINAD, and consumed 242 μW/channel dynamic power. An individual ADC channel is only 22 μm wide. COPSSAR ADCs are a factor of 4, 2, and 2.5 more area efficient than Multiple-ramp Single-slope ADCs, SAR ADCs, and Cyclic ADCs.& 2015 Elsevier Ltd. All rights reserved. MotivationColumn-parallel ADCs are frequently used in CMOS imagers to achieve fast frame rates. The key parameters for the design of these ADCs include area, pitch, speed, and quantization resolution. The single-slope architecture is often used because of the simple circuitry in each channel. But the conversion rate for this type of ADC is usually less than 1 MSPS, because the full-scale conversion time doubles with each additional bit [1,2]. In comparison, successive approximation register (SAR) ADCs can perform faster conversions at moderate to high resolution because the conversion time scales linearly with the number of bits. The disadvantage of SAR ADCs, however, is that they rely on a DAC to produce reference voltages. Usually a high-resolution high-linearity SAR ADC requires a large silicon area for capacitors in the DAC, making it unsuitable for column-parallel applications.One way to mitigate the large area requirement of SAR ADCs is to use the subranging technique. First a coarse conversion is performed to determine the M most significant bits. Then a fine conversion is performed over the subrange determined by the coarse conversion to calculate the K least significant bits. One way of implementing this second conversion is using a capacitor-array DAC to resolve voltages between two reference voltages that are generated with a resistor ladder [3]. When building an array of column-parallel ADCs, this resistor ladder can be shared by all of the channels. The area can be further reduced by using the same capacitor-array DAC to perform both the coarse and fine conversions, but in order to guarantee a correct coarse conversion for any inputs, the DAC must be accurate to the full resolution of the conversio...

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“…It is a key in the design of such an ADC to take into consideration the trade-off among area, resolution, power dissipation and conversion speed. For conventional high-speed CMOS image sensor, an in-pixel ADC [2][3][4], column-parallel cyclic ADC [8] and column-parallel successive approximation (SAR) ADC [1] have been reported. However, these architectures require a large circuit area.…”

Section: B Parallel Adcmentioning

confidence: 99%

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure

Kiyoyama

Fukushima

et al. 2010

2010 IEEE International 3D Systems Integration Conference (3DIC)

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In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure.In proposed system, one block consists of 3 stacked layers which are 100 pixels image sensor, CDS circuit, and one ADC. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area, ADC is required. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. ADC designed in the test chip for functional evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. The proposed 9-bit ADC was designed in 90-nm CMOS technology, and achieved power dissipation less than 0.5mW with supply voltage of 1.0V and 4 MS/s conversion rate. The circuit area is 100 ×100 ȝm 2 .

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A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters

Cited by 116 publications

References 10 publications

Uncertainty Visualization of Estimated Damage Using Kriging Model: Application to Time-Domain Reflectometry Sensing

Uncertainty Visualization of Estimated Damage Using Kriging Model: Application to Time-Domain Reflectometry Sensing

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure

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