A High-Speed and Ultra Low-Power Subthreshold Signal Level Shifter

Maghsoudloo, Esmaeel; Rezaei, Masoud; Sawan, Mohamad; Gosselin, Benoît

doi:10.1109/tcsi.2016.2633430

Cited by 56 publications

(26 citation statements)

References 11 publications

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“…The power dissipation and propagation delay of advanced DCVS based level shifter obtained during the preliminary analysis is 99.9 pW and 250 pS, respectively. The generalized circuit diagram for current mirror based level shifter [6] design is given in figure 1.10. It consists of a basic current mirror composed of transistor Q1 and Q2.…”

Section: Level Shifter Circuitsmentioning

confidence: 99%

Voltage Level Shifter Circuits in 45nm CMOS Technology - A Review

Aneesh¹

2019

IJRASET

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This paper demonstrates different voltage level shifter circuits in 45nm CMOS technology. In digital electronics the level shifter is also called as logic level shifter. It is a circuit used to translate signals from one logic level or voltage domain to another logic level or voltage domain. It allows compatibility between different blocks of system-on-chip (SoC) designs with different voltage requirements. The level shifter circuits are compared in terms of voltage shifting level, power dissipation and delay. The input signal isset to 0.3V. The dual supply voltages VDDH is set to 1.1V and VDDL is set to 0.3V. Simulations have been carried out in cadence® EDA tool.

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Section: Level Shifter Circuitsmentioning

confidence: 99%

Voltage Level Shifter Circuits in 45nm CMOS Technology - A Review

Aneesh¹

2019

IJRASET

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“…Ref. [16] proposed using a level-shifting capacitor to increase the conversion range, achieving a delay of 29ns with a power consumption of 61.5nW when the supply voltages, VDDL and VDDH, are 0.4V and 1.8V, respectively. Ref.…”

Section: Introductionmentioning

confidence: 99%

A Sub-100mV Ultra-Low Voltage Level-Shifter Using Current Limiting Cross-Coupled Technique for Wide-Range Conversion to I/O Voltage

et al. 2020

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In this paper, a sub-100mV ultra-low-voltage level-shifter for wide-range voltage conversion to I/O voltage is presented. The level-shifter uses a current limiting diode-connected transistor with crosscoupled transistor structure to reduce the minimum input voltage down to 100mV while covering a wide output voltage range up to I/O supply voltage (3V). We propose an improved split-control output buffer to reduce the static current from VDDH to VSS. The level-shifter is implemented using X-FAB 180nm HV CMOS process. The post-layout simulations show that the proposed structure achieves an average propagation delay of 7.57µs with a power consumption of 3.43nW when the supply voltages VDDL, VDDH, and input frequency are 100mV, 3V, and 1kHz, respectively. The design occupies 182.46µm 2 silicon area with a static power consumption of 3nW when VDDL and VDDH are 100mV and 3V, respectively, which is suitable for low power applications. INDEX TERMS Differential cascode voltage switch, level-shifter, low power, sub-threshold voltage, wide voltage range

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“…Several LSs have been proposed to get over the restrictions of traditional architectures. The LSs proposed in [12,13,14,15,16,17,18,19,20,21,22,23] employ CM-based structures. To minimize leakage power in standby mode, [12] cuts off the static current by a feedback PMOS.…”

Section: Introductionmentioning

confidence: 99%

A fast and low-power level shifter for multi-supply voltage designs

Yin

Jia

You

et al. 2020

IEICE Electron. Express

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This paper proposes a high-speed and ultra-low power level shifter (LS) capable of realizing wide-range voltage level conversion. Two key features are contained in the presented LS to support its superior performances. First, a novel boost control circuit is proposed to boost input voltage and strengthen pull-down driven capability, which results in significant improvement of operation speed and conversion range. Second, multi-threshold COMS (MTCMOS) and sub-threshold device sizing techniques are employed to reduce the static current, thereby obtaining ultra-low leakage power consumption. Post-layout simulation results demonstrate that the proposed LS implemented with SMIC 55-nm technology can convert 140mV lowvoltage to 1.2V. Meanwhile, when evaluated with the low supply voltage of 0.3V at 1MHz frequency, the transition energy of the presented LS is 87.35 fJ. Moreover, the static power consumption and propagation delay are only 64.2 pW and 18.07ns, respectively.

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A High-Speed and Ultra Low-Power Subthreshold Signal Level Shifter

Cited by 56 publications

References 11 publications

Voltage Level Shifter Circuits in 45nm CMOS Technology - A Review

Voltage Level Shifter Circuits in 45nm CMOS Technology - A Review

A Sub-100mV Ultra-Low Voltage Level-Shifter Using Current Limiting Cross-Coupled Technique for Wide-Range Conversion to I/O Voltage

A fast and low-power level shifter for multi-supply voltage designs

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