A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$0.18~\mu $ &lt;/tex-math&gt;&lt;/inline-formula&gt;m CMOS

Liu, Maliang; Zhu, Zhangming; Yang, Yong

doi:10.1109/tvlsi.2014.2386332

Cited by 19 publications

(17 citation statements)

References 11 publications

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“…A straightforward comparison is difficult as operating voltages, FS output current vary across these solutions and often CS-DACs target a resistive load. Although this TRI-DAC sampling rate is lower than reported DACs, the DNL/INL, area, SFDR and figureof-merit (FOM) performance is seen to be comparable to [12]- [14], and [15]. Furthermore, the output-impedance related HD3/SFDR performance for TRI-DAC is improved using combined impedance matching and capacitive compensation technique over a wide bandwidth without complex analog/digital calibrations.…”

Section: Layout and Simulation Resultsmentioning

confidence: 86%

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Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Mehta

O’Hare²,

O'Brien

et al. 2020

IEEE Open J. Circuits Syst.

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This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ∼ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.

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Section: Layout and Simulation Resultsmentioning

confidence: 86%

“…By placing the coefficients of sin(ωt) and sin(3ωt) from (15) in (17), the signal-dependent output-impedance related HD3 for BI-DAC yields…”

Section: ) Bi-dac Hd3 With Resistive Loadmentioning

confidence: 99%

Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Mehta

O’Hare²,

O'Brien

et al. 2020

IEEE Open J. Circuits Syst.

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show abstract

“…In this design, by using the method in reference [15,17], four groups of optimal switching sequence for 15 unary current sources are obtained, which are superior to the sequential sequence and symmetrical sequence in term of INL and variance, as shown in Table 1. When calculating the INL and variance of different switching sequences, it is assumed that the error sequence corresponding to the sequential sequence [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] is Although the switching sequence optimization can reduce the gradient error, the random error still exists, and DEM technique is a feasible solution for such situation. The core operation of DEM is carried out by the scrambler, which executes the process of randomly mapping the inputs to the outputs.…”

Section: Partial Randomization Dynamic Element Matching Based On Switmentioning

confidence: 99%

“…The switching sequence corresponding to the above mapping relationship is [8,6,10,4,12,2,14,15,1,13,3,11,5,9,7], which is one of the four optimized configurations. In general, PRDEM based on switching sequence optimization achieves simultaneous suppression of systematic and random errors with less design complexity, and the matching requirements for the current sources is relieved.…”

Section: Partial Randomization Dynamic Element Matching Based On Switmentioning

confidence: 99%

“…The dynamic element matching (DEM) technique, featuring the random selection of current sources, can be employed to mitigate the mismatch effect and relax the matching requirement for current sources, enabling the use of small transistors, thus allowing a more compact design of the Electronics 2019, 8, 464 2 of 11 current cells. This results in shorter wires and smaller parasitic capacitance, which are beneficial to reduce the errors caused by the switching operation of the internal current sources [6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

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A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

Wang¹,

Guo²,

Zhou³

et al. 2019

Electronics

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A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) fabricated in 55 nm complementary metal–oxide–semiconductor (CMOS) technology has been presented. A partial randomization dynamic element matching (PRDEM) method based on switching sequence optimization is proposed to mitigate the mismatch effect and suppress the harmonic distortion with low hardware complexity. In the switching current cell, the cascode structure together with “always-ON” small current sources are used to keep the output impedance high and uniform. A compact layout of the switching current array is carefully designed, featuring short wires routing and small parasitic capacitance. According to the measured results at 3GS/s, this DAC demonstrates a spurious-free dynamic range (SFDR) of 74.64 dBc at low frequency and 50 dBc at 1.5 GHz output. The chip occupies an active area of 0.2 × 0.48 mm2 and consumes a total power of 495 mW.

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Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters

Babaei

Hashemipour

2020

Circuit Theory & Apps

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SummaryIn this paper, a two‐dimensional dynamic element matching digital to analog converter (2D DEM DAC) is proposed having less design complexity compared to the conventional 2D DEM DAC. A novel unit element selection algorithm is presented in order to alleviate the need for consecutive elements selection that is mandatory in the conventional 2D DEM DAC. The flexibility of this algorithm leads to the introduction of a generalized multidimensional DEM DAC applicable to any resolutions. The multidimensional structure mitigates intersegment mismatch error and improves the spurious‐free dynamic range (SFDR) and intermodulation distortion (IMD). A 12‐bit 2D DEM DAC is simulated in 65‐nm CMOS process using the digital return‐to‐zero (DRZ) technique with 1.2 V of supply voltage and power dissipation of 26 mW. The simulation results show 63.4‐ and 60.71‐dB SFDR at near DC and Nyquist frequency, respectively, and <−61‐dB IMD with 1.25‐GHz sampling frequency.

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A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in <inline-formula> <tex-math notation="LaTeX">$0.18~\mu $ </tex-math></inline-formula>m CMOS

Cited by 19 publications

References 11 publications

Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters

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