A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process

Madsen, Kristian; Gathman, Timothy D.; Daneshgar, Saeid; Oh, Thomas C.; Li, James Chingwei; Buckwalter, James F.

doi:10.1109/jssc.2015.2472642

Cited by 31 publications

(13 citation statements)

References 20 publications

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“…The expressions are the same as those derived in [10,13], which confirm the correctness of the analysis above.…”

Section: Conflicts Of Interestsupporting

confidence: 79%

“…In track mode, high-level Track signal switches on transistor Q2 and low-level Hold signal turns off Q1, thus steering tail current ISEF to Q3. The switch In traditional designs, small-scale sampling capacitance is usually utilized in the track-hold switch, to achieve low distortions at the cost of deteriorating the feedthrough performance and hold-mode voltage drop [10]. It is rather difficult to make appropriate trade-offs among these properties at the same time.…”

Section: Sha Architecturementioning

confidence: 99%

“…First, most of the current sampling switches are based on switched emitter follower (SEF), which is simple in structure and easy to be realized. However, they suffer from high distortions [10][11][12]. Usually, a small-scale sampling capacitor is implemented to suppress harmonic distortion.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Ding

Zheng

et al. 2019

Electronics

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This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.

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“…The expressions are the same as those derived in [10,13], which confirm the correctness of the analysis above.…”

Section: Conflicts Of Interestsupporting

confidence: 79%

Section: Sha Architecturementioning

confidence: 99%

See 1 more Smart Citation

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Ding

Zheng

et al. 2019

Electronics

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“…The clock jitter/skew issues may be alleviated, too. Various high‐speed THA's have been implemented in either silicon or compound semiconductor technologies. In time‐interleaved ADCs, multiple THA's may be necessary to sample multiple parallel branches of multiplex input signal.…”

Section: Introductionmentioning

confidence: 99%

An 8 GS/s 20 GHz bandwidth master‐slave track‐and‐hold amplifier in 65 nm CMOS

Mehmood

Kang

et al. 2018

Micro & Optical Tech Letters

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A 65 nm CMOS fully-differential track-and-hold amplifier (THA) in master-slave configuration is presented. For highspeed operation, Cherry-Hooper amplifier with input inductive-peaking and switched-source follower (SSF) circuit are used for the front-end preamplifier and master/slave track-and-hold circuits, respectively. On-wafer testing in single-ended input/output configuration shows that the fabricated THA exhibits 20 GHz switched-mode bandwidth and 11.9 dB conversion gain at 8 GS/s clock, with THD < −36 dB and SFDR >36 dB within the 3-dB bandwidth, while consuming 361 mW of dc power at 2.6 V supply. This work represents the highest input bandwidth for master-slave THA in CMOS, to the best of authors' knowledge. The chip area is 0.681 mm 2 including pads (active chip area: 0.2 mm 2 ). K E Y W O R D Shigh speed sampling, master-slave THAs, sampling circuits, switched source follower, track and hold amplifier

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“…There are CMOS design examples, in which these switching pulses are generated such as in [4] to achieve a design with higher sampling rate, low noise, and high reliability. SiGe or InP based fabrication technologies are also preferred for that purpose [14][15][16]. Moreover, using different ADC architectures for each channel may be another possible solution.…”

Section: Introductionmentioning

confidence: 99%

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Aytar

Tangel

Afacan

2017

Journal of Electrical Engineering

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This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

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A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process

Cited by 31 publications

References 20 publications

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

An 8 GS/s 20 GHz bandwidth master‐slave track‐and‐hold amplifier in 65 nm CMOS

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

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