A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs

Giri, Chandan; Sarkar, Soumojit; Chattopadhyay, Santanu

doi:10.1109/vlsisoc.2007.4402522

Cited by 17 publications

(5 citation statements)

References 11 publications

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“…The simulation is done on MATLAB 14 and LPSOLVE. Comparison of the proposed algorithm with a reference method [19][20][21][22][23][24][25][26] is shown in Table 3 with SoC d695, g1023, p22810, and p93791. Table 3 shows the simulation results for sessionbased test scheduling.…”

Section: Results Discussionmentioning

confidence: 99%

Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors

Parmar

Mehta

2020

Lecture Notes in Electrical Engineering

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As circuit size increases with scale down in technology, the time required to test the circuits also increases. Scheduling of the cores is a very effective technique to reduce the test time of a system-on-chip (SoC) in the given power budget. As the frequency is relative to the power and the test time, by controlling the test clock frequency, the power consumption and the test time per core can be adjusted to yield an optimal solution to the test scheduling problem. In traditional methods, the fixed test clock frequency is applied to all the test vectors of a given core in case of power-aware test scheduling. Whereas in the proposed plan, a power-aware dynamic frequency allocation is done to individual scan vector of the core. Session-based test scheduling scheme is implemented to reduce test time. Results show the improvement up to 58% with session-based test scheduling is achieved over the existing solution for the benchmark SoCs with minor bit and area overhead.

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Section: Results Discussionmentioning

confidence: 99%

Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors

Parmar

Mehta

2020

Lecture Notes in Electrical Engineering

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“…According to Darwin's theory, the fittest individuals are more likely to survive in nature [5]. Genetic Algorithms (GA) work on solution representation in binary format, whereas evolution strategies and differential evolution support solutions with absolute values [6]. The GA implementation methodology is of two levels.…”

Section: Literature Reviewmentioning

confidence: 99%

Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm

et al. 2022

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System-on-Chip (SoC) is a structure in which semiconductor components are integrated into a single die. As a result, testing time should be reduced to achieve a low cost for each chip. Effective test scheduling can reduce the SoC testing time, which is more challenging due to its complexity. In this paper, the modified BAT algorithm-based test scheduling is proposed. Testing is carried out on the SoC ITC'02 benchmark circuits. The Modified Bat method is a recently heuristic algorithm that performs global optimization by imitating bat echolocation. Compared to other state-of-the-art algorithms, the Modified BAT Optimization method reduces testing time on SoCs. This paper improves the algorithm's exploration process by adjusting the equation for bat loudness (A0) and pulse emission rate (r). The modified BAT algorithm converges to the optimal solution faster. It has been used in 14 international standard test functions. The test results indicate that the modified BAT algorithm has a fast convergence speed, which minimizes the testing time compared to other evolutionary algorithms on the ITC'02 SoC benchmark circuits.

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“…In this algorithm, virtual pheromones generated by the artificial ants are used for updating the path. The density and the amount of pheromone are the major factors that affect their path updating [25,26]. It depends on the comparison of the quality of the pheromone with the former artificial ant of the same iteration.…”

Section: Ant Colony Optimisationmentioning

confidence: 99%

Optimal design of adaptive power scheduling using modified ant colony optimization algorithm

Joy

Krishnakumar

2020

IJECE

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For generating and distributing an economic load scheduling approach, artificial neural network (ANN) has been introduced, because power generation and power consumption are economically non-identical. An efficient load scheduling method is suggested in this paper. Normally the power generation system fails due to its instability at peak load time. Traditionally, load shedding process is used in which low priority loads are disconnected from sources. The proposed method handles this problem by scheduling the load based on the power requirements. In many countries the power systems are facing limitations of energy. An efficient optimization algorithm is used to periodically schedule the load demand and the generation. Ant colony optimization (ACO) based ANN is used for this optimal load scheduling process. The present work analyse the technical economical and time-dependent limitations. Also the works meets the demanded load with minimum cost of energy. Inorder to train ANN back propagation (BP) technics is used. A hybrid training process is described in this work. Global optimization algorithms are used to provide back propagation with good initial connection weights.

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A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs

Cited by 17 publications

References 11 publications

Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors

Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors

Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm

Optimal design of adaptive power scheduling using modified ant colony optimization algorithm

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