Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors

Abstract

As circuit size increases with scale down in technology, the time required to test the circuits also increases. Scheduling of the cores is a very effective technique to reduce the test time of a system-on-chip (SoC) in the given power budget. As the frequency is relative to the power and the test time, by controlling the test clock frequency, the power consumption and the test time per core can be adjusted to yield an optimal solution to the test scheduling problem. In traditional methods, the fixed test clock frequency is applied to all the test vectors of a given core in case of power-aware test scheduling. Whereas in the proposed plan, a power-aware dynamic frequency allocation is done to individual scan vector of the core. Session-based test scheduling scheme is implemented to reduce test time. Results show the improvement up to 58% with session-based test scheduling is achieved over the existing solution for the benchmark SoCs with minor bit and area overhead.