Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm

Abstract

System-on-Chip (SoC) is a structure in which semiconductor components are integrated into a single die. As a result, testing time should be reduced to achieve a low cost for each chip. Effective test scheduling can reduce the SoC testing time, which is more challenging due to its complexity. In this paper, the modified BAT algorithm-based test scheduling is proposed. Testing is carried out on the SoC ITC'02 benchmark circuits. The Modified Bat method is a recently heuristic algorithm that performs global optimization by imitating bat echolocation. Compared to other state-of-the-art algorithms, the Modified BAT Optimization method reduces testing time on SoCs. This paper improves the algorithm's exploration process by adjusting the equation for bat loudness (A0) and pulse emission rate (r). The modified BAT algorithm converges to the optimal solution faster. It has been used in 14 international standard test functions. The test results indicate that the modified BAT algorithm has a fast convergence speed, which minimizes the testing time compared to other evolutionary algorithms on the ITC'02 SoC benchmark circuits.

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“…Furthermore, each agent in the swarm is capable of traveling to a prior best position that the swarm previously discovered or locating the most "nutritious" locations. The BA has demonstrated exceptional effectiveness in solving continuous optimization issues [43].…”

“…After the bats' positions are updated, a random number is formed; if the random number is greater than the pulse emission rate r i , a new location will be generated around the most effective solutions at the time. This new position may be represented by Eq (4) [43].…”