A fully-integrated GPS receiver front-end with 40 mW power consumption

Steyaert, Michiel; Coppejans, P.; Cock, Wouter De; Leroux, Paul; Vancorenland, P.

doi:10.1109/isscc.2002.993099

Cited by 23 publications

(7 citation statements)

References 1 publication

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“…The low-IF architecture can be further classified into single, dual, and triple downconversion architecture. Generally, a single downconversion architecture [2], [7], [8], [10], [11]- [13] is preferred, however [3], [6] have used double downconversion architecture, and [28] has used triple downconversion architecture. The dual downconversion low-IF architecture with non-zero IF is depicted in Fig.…”

Section: Gps Receiver Front End Architecturementioning

confidence: 99%

“…The CMOS process is the most commonly used technology for GPS receivers [10] - [25]. However, [26] has used bipolar technology and [8], [9], [30] have used the BiCMOS technology.…”

Section: B Off-chip Componentsmentioning

confidence: 99%

“…The sampling rate of the ADC in the low-IF receiver is limited by the bandwidth of the signal not the highest frequency component present in the signal. Based on the literature survey, the ADC used for the GPS receiver include 1-bit clocked comparator [3], [8], 2-4 bit charge pump-based ADC (Flash ADC) [6], [11], [33], [15] - [17], [22], [31] and several variants of sigma-delta ADC (SDADC) [7], [9], [10], [19], [41] - [44]. While [38] has used 9-bit SAR ADC.…”

Section: G Adcmentioning

confidence: 99%

“…The architecture of the bandpass SDADC can also be categorised into quadrature and non-quadrature topology. The quadrature SDADC differs from a low pass counterpart in terms of the complex bandpass loop filter [10]. The quadrature architecture is preferred over non-quadrature as it reduces the number of Op-amps and provides higher image rejection [19].…”

Section: G Adcmentioning

confidence: 99%

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Advanced System Analysis and Survey on the GPS Receiver Front End

Kumari

Bhatt

2022

IEEE Access

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A fully integrated GPS receiver system can enable unique system capabilities by synthesizing both receiver front end and baseband on the same chip, leading to lower area overhead and higher integration. A review on the GPS receiver system that focuses on front end design is presented in the paper. The first section discusses the various global navigation satellite system (GNSS), followed by the GPS working section. Afterwards, the paper discusses the previous works on the GPS receiver front end design. It provides a detailed survey and classification of various receiver architecture, including the LNA, mixer, filter, and ADC topologies. Besides, several image rejection techniques are presented for more than 50 GPS receivers. The various performance parameters of the GPS receiver front end in the literature are presented with the graphical view in the state-of-the-art discussion section. This literature survey provides the most extensive compilation to date of the various topologies, techniques and explains their implementation in the GPS receiver system. A new figure of merit that includes all the system parameters is proposed. The FOM can be an excellent reference to enhance the research work in the field of GPS receivers. In the end, the paper describes the possible research scope and challenges associated with the design of the GPS receiver front end.INDEX TERMS global navigation satellite system (GNSS), image rejection, RF front end, sensitivity, spurious free dynamic range (SFDR), wireless communication.

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Section: Gps Receiver Front End Architecturementioning

confidence: 99%

“…The CMOS process is the most commonly used technology for GPS receivers [10] - [25]. However, [26] has used bipolar technology and [8], [9], [30] have used the BiCMOS technology.…”

Section: B Off-chip Componentsmentioning

confidence: 99%

Section: G Adcmentioning

confidence: 99%

Section: G Adcmentioning

confidence: 99%

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Advanced System Analysis and Survey on the GPS Receiver Front End

Kumari

Bhatt

2022

IEEE Access

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“…This market demands a low-cost, single-chip realization [3]. Above all a low power consumption to maximize battery lifetime will be the main constraint.…”

Section: Introductionmentioning

confidence: 99%

An Ultra Low Voltage, Low Power, Fully Integrated VCO for GPS in 90 nm RF-CMOS

Aspemyr

Linten

2005

Analog Integr Circ Sig Process

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A fully integrated 0.6 V VCO for the GPS L1 band is realized in a 90 nm RF-CMOS process. The purpose of the design is to demonstrate how suitable deep submicron CMOS transistors are for ultra low voltage, low power oscillator design. The VCO operates at 6.3 GHz and a divide-by-four circuit buffer provide the wanted 1575.42 MHz signal. Measured phase noise is for a 0.6 V supply voltage and bias current of 2.6 mA −122 dBc/Hz at 1 MHz offset, measured for a 1.58 GHz carrier. The phase noise of the VCO has been measured for different bias point showing good agreement between measured results and theory.

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