An Ultra Low Voltage, Low Power, Fully Integrated VCO for GPS in 90 nm RF-CMOS

Aspemyr, Lars; Linten, Dimitri

doi:10.1007/s10470-005-4077-5

Cited by 9 publications

(4 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to satisfy the need of designers, different types of inductors are proposed in the technology design-kit ('Ind_Sym_la', 'Ind_Sym_mf', 'Ind_dif_la', etc.). Furthermore, the used technology provides differential inductance that is also more appropriate to design differential structure [12]. Indeed, the differential inductor results in chip area saving compared to two single-ended inductors.…”

Section: ▪ Inductance Optimization Strategymentioning

confidence: 99%

Ultra-low-power wideband NMOS LC-VCO design for autonomous connected objects

Ghorbel

Haddad

Rahajandraibe

et al. 2020

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

In this paper, a fully integrated subthreshold LC voltage controlled oscillator (VCO) is presented. A design methodology is also proposed to find the optimal parameters lowering the power consumption. This methodology has been applied to design oscillators for different frequency bands. Furthermore, an adaptive body biasing technique has been used to improve the startup constrains and allows a high immunity to PVT (process, voltage and temperature) variations. A VCO operating in 5 GHz ISM (Industrial, Scientific and Medical) band has been realized with the proposed methodology in 0.13μm CMOS. It consumes only 468 μW from 0.39V supply voltage. This makes it possible to meet the required specifications of autonomous connected objects and IoT applications. The measured oscillation frequency can be tuned from 5.14 GHz to 5.44 GHz. The obtained phase noise is approximately equal to -112 dBc/Hz in post-layout simulation (PLS) and -104.5 dBc/Hz in measure.

show abstract

Section: ▪ Inductance Optimization Strategymentioning

confidence: 99%

Ultra-low-power wideband NMOS LC-VCO design for autonomous connected objects

Ghorbel

Haddad

Rahajandraibe

et al. 2020

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…The inductor is one of the most essential component in an LC-tank oscillator, since its quality factor affects the phase noise performances and determines the power dissipation. The inductor was implemented differentially and provides two advantages over its single-ended counterpart [15]. First, the differential inductor results in saving in chip area compared to two single-ended inductors.…”

Section: A the 025 µM Rf-bicmos Sige Technologymentioning

confidence: 99%

Design and implementation of a 6-GHz array of four differential VCOs coupled through a resistive network

Mellouli

Cordeau

Mnif

et al. 2013

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper presents the design and the implementation of a fully monolithic coupledoscillator array, operating at 6 GHz with close to zero coupling phase, in 0.25 µm BICMOS SiGe process. This array is made of four LC-NMOS differential VCOs coupled through a resistor. The single LC-NMOS VCO structure is designed and optimized in terms of phase noise with a graphical optimization approach while satisfying design constraints. At 2.5 V power supply voltage, and a power dissipation of only 125 mW, the coupled oscillators array features a simulated phase noise of-127.3 dBc/Hz at 1 MHz frequency offset from a 6 GHz carrier, giving a simulated phase progression that was continuously variable over the range-64° < Δ <64 ° and-116° < Δ < 116°. This constant phase progression can be established by slightly detuning the peripheral array elements, while maintaining mutual synchronization.

show abstract

“…In a classical charge pump PLL (CPPLL) system [9][10][11][12][13][14][15], phase noise is mainly generated from two parts: out-of-band noise which is dominated by the voltage-controlled oscillator (VCO) (noise of low pass filter is neglected); and in-band noise which is dominated by the phase detector, charge pump and divider. Several efforts have been addressed to study the phase noise of VCOs [16][17][18] and designs with ultra-low power consumption have been published [19][20][21]. Hence, this paper concentrates on the improvement of in-band noise at low supply voltage.…”

Section: Introductionmentioning

confidence: 99%

A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM

Zuo

Zhao

Zhou

2021

Sensors

View full text Add to dashboard Cite

This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and −251.6 dB FoM.

show abstract

An Ultra Low Voltage, Low Power, Fully Integrated VCO for GPS in 90 nm RF-CMOS

Cited by 9 publications

References 18 publications

Ultra-low-power wideband NMOS LC-VCO design for autonomous connected objects

Ultra-low-power wideband NMOS LC-VCO design for autonomous connected objects

Design and implementation of a 6-GHz array of four differential VCOs coupled through a resistive network

A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM

Contact Info

Product

Resources

About