Two 1-1-1 MASH time-to-digital converters (TDCs) are presented in this paper. Third-order time domain noise-shaping has been adopted by the TDCs to achieve better than 6 ps resolution. Following a detailed analysis of the noise generation and propagation in the MASH structure, the first prototyping TDC has been realized in CMOS technology. It achieves an ENOB of 11 bits and consumes 1.7 mW from a 1.2 V supply. In the second MASH TDC, a delay-line assisted calibration technique is introduced to mitigate the phase skew caused by the large comparator delay, which is the main limiting factor of the MASH TDC's resolution. The demonstrated TDC achieves an ENOB of 13 bits and a wide input range of 100 ns. This TDC shows a temperature coefficient of within a temperature range of to. It consumes only 0.7 mW and occupies area (core).
Abstract-Total Ionizing Dose (TID) effects are studied on a radiation hardened by design (RHBD) 256x256-pixel CMOS image sensor (CIS) demonstrator developed for ITER remote handling by using X and γ-rays irradiations. The (color) imaging capabilities of the RHBD CIS are demonstrated up to 10 MGy(SiO2), 1 Grad(SiO2), validating the radiation hardness of most of the designed integrated circuit. No significant sensitivity (i.e. responsivity and color filter transmittance) or readout noise degradation is observed. The proposed readout chain architecture allows achieving a maximum output voltage swing larger than 1 V at 10 MGy(SiO2). The influence of several pixel layout (the gate oxide thickness, the gate overlap distance and the use of an in-pixel P+ ring) and manufacturing process parameters (photodiode doping profile, process variation) on the radiation induced dark current increase is studied. The nature of the dark current draining mechanism used to cancel most of the radiation induced degradation is also discussed and clarified.
Recently, high-resolution TDCs have gained more and more popularity due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs [1, 3], pipeline TDCs [2], and SAR TDCs [4]. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to achieve sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused by process variation limits its effectiveness, and the same holds for the time amplification method. The gated-ring-oscillator (GRO) method [5] is introduced to achieve sub-ps time resolution, but it still requires an equivalent CMOS gate delay as low as 6ps. Upcoming applications in 4 th-generation nuclear reactors, space, and high-energy physics such as the large Hadron collider (LHC), require the TDC to achieve a high time resolution in harsh environments with high temperature and radiation, where the threshold voltage, transconductance, and delay of a transistor undergo dramatic changes. In these cases, the high accuracy and robustness of the TDC need to be inherent to the design rather than by employing a fast CMOS technology.
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