A fully integrated 13 GHz ΔΣ fractional-n PLL in 0.13 μm CMOS

Tiebout, M.; Sandner, C.; Wohlmuth, H.-D.; Dalt, Nicola Da; Thaller, Edwin

doi:10.1109/isscc.2004.1332756

Cited by 11 publications

(11 citation statements)

References 7 publications

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“…Since quantization noise of such fractional spur reduction circuits can fold into and corrupt the PLL spectrum via loop nonlinearities, more efforts are required to minimize loop nonlinearities [2], [14]- [16]. This design complexity is compounded by the fact that the negative impact of the quantization noise is hard to predict [17]. In contrast, the design of integer-PLLs is much less complex due to the absence of fractional spurs.…”

Section: A Feature 1-simultaneous Achievement Of Fast Locking and Dementioning

confidence: 99%

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

Woo

Liu

Nam

et al. 2008

IEEE J. Solid-State Circuits

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Abstract-We introduce a single-loop PLL that operates in a narrower-bandwidth, integer-mode during phase lock and in a wider-bandwidth, fractionalmode during transient. This hybrid PLL, as a generalization of the conventional variable-bandwidth PLL that shifts only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional-PLL and design simplicity of the integer-PLL, and as such, brings benefits in certain important PLL applications. In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching. A CMOS IC prototype attests to the validity of the proposed approach.Index Terms-Charge-pump phase-locked loops, fractionalfrequency synthesizers, integer-frequency synthesizers, phaselocked loops.

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Section: A Feature 1-simultaneous Achievement Of Fast Locking and Dementioning

confidence: 99%

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

Woo

Liu

Nam

et al. 2008

IEEE J. Solid-State Circuits

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“…It is also difficult to acquire an accurate model for the accumulation MOS capacitor [7]. Another way to improve the linearity of a varactor is to combine P-type and N-type varactors in a differentially controlled PLL [8]. However, such a differential loop filter incurs a prohibitively large die area cost for low loop bandwidth LC-VCO PLLs.…”

Section: A Averaging Varactormentioning

confidence: 99%

“…Typically the inductance has a very small frequency dependent coefficient, therefore, (7) also indicates that making constant would maintain a constant loop bandwidth 2 over the entire PLL tuning range. Specifically, the following conditions (8) and (9) would maintain a constant loop bandwidth.…”

Section: Introductionmentioning

confidence: 99%

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

Hanumolu

Mayaram

et al. 2009

IEEE J. Solid-State Circuits

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An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The combination of these techniques maintains a constant loop bandwidth over a wide range of operating frequencies. Fabricated in a 0.13 m CMOS technology, the prototype chip measures less than 4% variation in VCO CP (equivalent to the variation in PLL loop bandwidth) for an operating frequency range of 3.1 to 3.9 GHz. Index Terms-Bandwidth tracking, frequency synthesizer, LC-VCO, loop bandwidth, phase-locked loop (PLL).

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“…The implementation of a multi-modulus divider at Kuband is a primary challenge for low-power fractional-N synthesis, and can dominate the overall power consumption [4]. A 0.18µm BiCMOS technology can not support power efficient phase-switching dividers [8] at Ku-band, and the bias current required for ECL dividers is prohibitively large.…”

Section: B Prescaler and Multi-modulus Dividersmentioning

confidence: 99%

A 16mW 8Mbps Fractional-N FSK Modulator at 15.8-18.9GHz

Straayer

Messier

Hancock

2007

2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium

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Indirect modulation of fractional-N synthesizers is an energy-efficient architecture capable of moderate data rates, and is well-suited for use in sensor networks or WLAN. Although the architecture is used primarily at low RF frequencies, the capability for fractional-N synthesizers at Ku-band and above currently exist in available silicon technology. Recent demonstrations at 10-25GHz show promising results, although power consumption at this higher frequency remains high for small batterypowered devices. This work implements a fully-integrated fractional-N synthesizer optimized for power efficient modulation at 15.8 to 18.9GHz with an 80MHz reference. Binary and 4-ary FSK modulation of up to 8Mbps is achieved while consuming 16mW in IBM 0.18µm SiGe BiCMOS.

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A fully integrated 13 GHz ΔΣ fractional-n PLL in 0.13 μm CMOS

Cited by 11 publications

References 7 publications

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

A 16mW 8Mbps Fractional-N FSK Modulator at 15.8-18.9GHz

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