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We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.

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A bstmctA completely integrated 19 GHz static 2:l frequency divider in 120nm CMOS is presented. The divider operates up to 19GHz and features an enhanced input sensitivity of 0 dBm over a broad input band of 15 GHz. The circuit draws 44mA from a single 1.5V supply. To drive 50R loads up to 9.5GHz, an output buffer is also included in the divider circuit.

A new method for characterization of nionolithic lumped planar transformers is proposed in this paper. A lumped low-order equivalent; model is derived from the physical layout using a new expression for the substrate loss. Two transformers are considered in detail, showing excellent agreement between simulation and ineasurement. sc1