A Fully Integrated 1.2V LDO Regulator

Abugharbieh, Khaldooon; Yaseen, Basel; Deeb, Abdullah

doi:10.1109/icm50269.2020.9331816

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…This makes necessary the introduction of transient enhancement circuit techniques to balance the dynamic performance with a minimum effect on power efficiency and circuit complexity. There is extensive research on low dropout regulators for portable applications by taking advantage of the miniaturization of CMOS technology [17][18][19][20][21][22][23][24][25][26]. However, some of them report load capacitor values that do not comply with the size constraint of portable SoC devices ( [17] and [18] report external load capacitors of 1 µF and 3 nF, respectively).…”

Section: Introductionmentioning

confidence: 99%

“…However, some of them report load capacitor values that do not comply with the size constraint of portable SoC devices ( [17] and [18] report external load capacitors of 1 µF and 3 nF, respectively). Among those that are fully integrated, power consumption is jeopardized by quiescent currents too high to be used in short-lived battery-operated devices ( [19] reports 495 µA, [20] 188 µA, [21] 76 µA and [22] 265 µA). Other proposals enhance the transient response by using adaptive biasing but jeopardizing the circuit complexity and power consumption ( [23] increases the I q from 4.45 µA for I Load = 100 µA up to 130 µA for I Load = 100 mA; and the I q from [24] goes from 42.1 µA for I Load < 1 mA up to 108 µA I Load > 1 mA).…”

Section: Introductionmentioning

confidence: 99%

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A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

2021

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This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

2021

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Fully Integrated 1.8 V Output 300 mA Load LDO with Fast Transient Response

et al. 2023

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Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output power transistor, this LDO can quickly adjust the gate voltage of the power transistor without additional power consumption. By adding an active capacitor circuit composed of a fast comparator with offset voltage at the output point, this LDO can quickly charge/discharge the transient current and accelerate the transient response without reducing the circuit stability. Simulation results show that the proposed LDO has an output voltage of 1.8 V, when the input voltage is 2 V to 5 V while consuming 66.4 μA of quiescent current. The proposed capless LDO has a 1.94 µV/mA load regulation, a 0.55 mV/V linear regulation, and a −60 dB@1kHz power supply rejection. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO settles in 400 ns with an overshoot and undershoot of 67 mV and 86 mV, respectively.

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A Hybrid-Mode LDO Regulator with Fast Transient Response Performance for IoT applications

Mouzouade

Khadiri

Lakhliai

et al. 2021

Wseas Transactions on Power Systems

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A hybrid-mode low-drop out (LDO) voltage regulator with fast transient response performance for IoT applications is proposed in this paper. The proposed LDO regulator consist of two sections. First section is an analog regulator which includes a folded cascode operational amplifier to achieve good PSRR. Second section is current DAC and detectors whitch includes a cource current DAC, sink current DAC, undershoot detectors, and overshoot detectors. The current DAC and detectors are designed to obtain a low drop out and fast transient response. The proposed hybrid-mode LDO voltage regulator has been designed, simulated and layouted in Cadence using TSMC 90 nm CMOS technology. The input range of the LDO regulator is 1.2–2.0 V, and it can produces an output voltage of 1.2V. The LDO regulator achieves 58uA quiescent current, -69 PSRR @ 1 KHz noise frequency and an output voltage drop of around 60mV for a load current step of 100 mA. The final design occupies approximately 0.09 mm2.

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A Fully Integrated 1.2V LDO Regulator

Cited by 3 publications

References 6 publications

A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

Fully Integrated 1.8 V Output 300 mA Load LDO with Fast Transient Response

A Hybrid-Mode LDO Regulator with Fast Transient Response Performance for IoT applications

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