A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

Pérez-Bailón, J.; Calvo, B.; Medrano, N.

doi:10.3390/electronics10172108

Cited by 10 publications

(4 citation statements)

References 39 publications

(55 reference statements)

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“…Moreover, even though the power of the AVC is included, the quiescent current of the entire DLDO is still very low, resulting in the two FoMs. Meanwhile, we provide a comparison of the related simulation results with the previous publications [1,2,23,24] in Table 4 regarding the analog LDOs in electronics. It can be seen from Table 4 that the static power consumption of the recent analog LDOs is comparable to that of the proposed DLDO.…”

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

Xin,

Wei,

Tong

2023

Electronics

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A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm2 in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works.

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Section: Simulation Results and Comparisonsmentioning

confidence: 99%

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

Xin,

Wei,

Tong

2023

Electronics

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“…Thus, γ accounts for the regulator's stability under minimum operating current conditions. Finally, the third FOM [25] considers the power efficiency, as well as the regulation performance (LNR and LDR), and is defined as:…”

Section: Comparisonmentioning

confidence: 99%

Three-Stage CMOS LDO with Optimized Power and Dynamic Performance for Portable Devices

Serrano-Reyes,

Sanz-Pascual,

Calvo-López

2023

Electronics

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Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that addresses these challenges by employing the reverse nested Miller compensation (RNMC) with current buffers embedded within the own class AB high gain error amplifier (EA) topology, and a time response enhancement circuit (TREC). High-gain (>120 dB) class AB EA renders good regulation performance with enhanced dynamic performance. The proposed compensation scheme improves the gain bandwidth product (GBW) and stability of the regulator, while the TREC reduces overshoot and undershoot during load transients without additional steady-state power consumption. Post-layout simulations confirm the robustness of the proposed 180 nm CMOS design across a wide range of operating conditions, achieving a regulated output voltage of 1.8 V with 100 mV dropout, good load and line regulating performance, and excellent load transient response with reduced undershoot and overshoot at minimum power (Iq = 13.8 μA) and area (314 μm × 150 μm) consumption. The proposed LDO regulator thus offers a compelling compromise between power consumption, area efficiency, and dynamic performance, making it highly suitable for portable applications.

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“…In analog devices, the stability of the reference voltage generated by the BGR block plays a vital role in the performance of the whole circuit. By way of illustration, the output voltage of the lowdropout regulator (LDO) linearly depends on the reference voltage [8]. Consequently, the ripple of BGR's output voltage directly affects the accuracy of LDO's output, which may affect the performance of the IC that uses LDO as the power supply.…”

Section: Introductionmentioning

confidence: 99%

Novel Methods for Improved Particle Swarm Optimization in Designing the Bandgap Reference Circuit

Hoang,

Quoc,

Zhang

et al. 2023

IEEE Access

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Bandgap reference (BGR) circuits play a crucial role as voltage reference generators for other components within a variety of analog integrated circuits. Therefore, their power supply rejection ratio (PSRR), which represents the BGR's ability to maintain a stable output in the presence of supply ripples, has a substantial impact on the overall circuit performance and is consequently worthy of attention. In this work, the design of a 65nm-CMOS BGR circuit and the computational approach to optimize its PSRR value are presented. Our proposed BGR circuit incorporates a modification in the op-amp structure to enhance the PSRR parameter. Detailed explanations of the proposed op-amp's differential gain calculation and the PSRR parameter formula are provided. Additionally, we employ the particle swarm optimization (PSO) algorithm to maximize PSRR while satisfying other specifications. Four distinct approaches for utilizing the inertia weight parameter of the PSO algorithm are explored: two newly developed techniques (PSO -local exploitation orienter (PSO-LEO) and PSO -global exploration orienter (PSO-GEO)) together with two conventional approaches. A comprehensive comparative analysis reveals the superiority of our proposed PSO-GEO technique. Ultimately, our 65 nm CMOS bandgap circuit exhibits exceptional performance, featuring a temperature coefficient of 6.4056 ppm/°C and a PSRR of 99.9896 dB at 1 kHz. In conclusion, this work contributes substantially through op-amp architecture modification, PSRR optimization via the PSO algorithm, and introducing new inertia weight parameter utilization strategies and analyzing them.

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A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

Cited by 10 publications

References 39 publications

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

Three-Stage CMOS LDO with Optimized Power and Dynamic Performance for Portable Devices

Novel Methods for Improved Particle Swarm Optimization in Designing the Bandgap Reference Circuit

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