The problem of the potential depletion of IPv4 addresses has given rise to the development of a new version of the Internet Protocol named IPv6. This version of the protocol offers many improvements, including an increase in the address space from 2 32 to 2 128 and improvements in security, mobility, and quality of service. However, the transition from the current version to the new version (IPv4 to IPv6) is complicated and cannot be performed in a short time. The size and complexity of Internet make this migration task extremely difficult and timeconsuming. The Internet Engineering Task Force (IETF) took into account this migration problem and proposed transition mechanisms as temporary solutions allowing IPv4 to coexist and operate in parallel with IPv6 networks. The dual stack, manual tunnel, and 6to4 automatic tunnel appear to be promising solutions depending on their characteristics and benefits. In this paper, we study the performance of these transition mechanisms on real-time applications (VoIP and Video Conferencing) using the network simulator OPNET Modeler. Performance parameters such as delay, delay variation, jitter, MOS, and packet loss are measured for these transition mechanisms. The obtained results showed that the dual stack transition mechanism gave better network performance than the tunneling mechanisms.
This paper presents an integrated power control system for photovoltaic systems based on maximum power point tracking (MPPT). The architecture presented in this paper is designed to extract more power from photovoltaic panels under different partial obscuring conditions. To control the MPPT block, the integrated system used the ripple correlation control algorithm (RCC), as well as a high-efficiency synchronous direct current (DC-DC) boost power converter. Using 180 nm complementary metal-oxide-semiconductor (CMOS) technology, the proposed MPPT was designed, simulated, and layout in virtuoso cadence. The system is attached to a two-cell in series that generates a 5.2 V average output voltage, 656.6 mA average output current, and power efficiency of 95%. The final design occupies only 1.68 mm2.
In this paper, we propose a new power generating circuit for passive ultra high frequency (UHF) RFID tag. The proposed power generating circuit consists of a RF limiter, a high power efficiency and high sensitivity full wave radio frequency (RF) wave rectifier and a low-power regulator with NMOS diodes work like a DC-limiter. The design method proposed in this study use one low drop out (LDO) regulator to provide tow output stable supply voltages vdd1 of value 1V for the digital section supply, and vdd2 of value 0.5V for the analog front-end section power supply. The proposed power generating circuit is optimized in terms of power consumption of RFID tag system to have a high operating range under conditions of 50 Ohm antenna, -24 dBm input RF power, 900MHz and 1 M DC, with low power dissipation and 29.15% large power conversion efficiency. The power generating circuit was designed, simulated and layouted in Cadence using TSMC 180 nm technology. The final design occupies approximately 0.25mm<sup>2</sup>.
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