A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection

Abstract

Real-time object detection is becoming necessary for a wide number of applications related to computer vision and image processing, security, bioinformatics, and several other areas. Existing software implementations of object detection algorithms are constrained in small-sized images and rely on favorable conditions in the image frame to achieve real-time detection frame rates. Efforts to design hardware architectures have yielded encouraging results, yet are mostly directed towards a single application, targeting specific operating environments. Consequently, there is a need for hardware architectures capable of detecting several objects in large image frames, and which can be used under several object detection scenarios. In this work, we present a generic, flexible parallel architecture, which is suitable for all ranges of object detection applications and image sizes. The architecture implements the AdaBoost-based detection algorithm, which is considered one of the most efficient object detection algorithms. Through both FPGA emulation and largescale implementation, and RTL synthesis and simulation, we illustrate that the architecture can detect objects in large images (up to 1024x768 pixels) with frame rates that can vary between 64-139 fps for various applications and input image frame sizes.

Image Feature Extraction Acceleration

“…Despite its simplicity and detection effectiveness, the algorithm still requires a considerable amount of computational and memory resources in terms of embedded system affordability. Different approaches have been proposed in the literature in order to increase the implementation performance: by exploiting the highly parallel computation structure of GPUs [17,18]; by making the most of the logic and memory capabilities of FPGAs [19,20]; by custom design of specialized digital hardware [21] etc. In order to evaluate the possibilities for focal-plane acceleration, our interest focuses on pixel-level operations.…”

A high-performance architecture for training Viola-Jones object detectors

“…Accordingly, there have been a number of implementations of the Viola-Jones algorithm on various hardware platforms [8,9,10].…”

System Architecture for Real-Time Face Detection on Analog Video Camera

“…The high-speed vision system developed so far accelerates the computing speed by using massively parallel processors [17,18] or by implementing the dedicated circuits in reconfigurable hardware platform [19][20][21][22][23][24][25]. However, the previous researches focused on the enhancement of the execution speed instead of the implementation on the feasible area, which is the real concern of embedded systems.…”