A Fast-Settling Integer-$N$  Frequency Synthesizer Using Switched-Gain Control

Zhao, Haixiang; Mandal, Soumyajit

doi:10.1109/tcsi.2019.2960752

Cited by 6 publications

(2 citation statements)

References 24 publications

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“…To accelerate the locking speed, there are three main technologies namely dynamic loop bandwidth [7][8][9][10][11][12], fractional-N frequency division [6,[13][14][15], feed-forward preset [16][17][18], and the emerging all-digital PLL (AD-PLL) [15,19]. Fractional-N technology can increase the reference frequency so that the loop bandwidth is no longer limited by the channel bandwidth and can be a larger value, and has been widely used.…”

Section: Introductionmentioning

confidence: 99%

A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

et al. 2021

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This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

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Section: Introductionmentioning

confidence: 99%

A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

et al. 2021

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“…The traditional structure's locking time is related to output frequency range, filter's bandwidth, target frequency, and frequency resolution. The larger the output frequency range is, the smaller the bandwidth of the filter is, the farther the target frequency is from the initial frequency, and the higher frequency resolution of DCO is, resulting in longer locking time [9][10][11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

A Novel Fast-Locking ADPLL Based on Bisection Method

Deng

Zhu

2021

Electronics

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Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.

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