A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Abstract

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

Wide-Band Low Phase-Noise Signal Generation Using Coaxial Resonator in Cascaded Phase Locked Loop

“…Combining both analog and digital functionalities, PLLs offer a balance between performance and cost. Recently, advancements in lithography have enabled the integration of PLL structures and high-frequency oscillators onto a single silicon wafer [4,10]. Leveraging established chip production processes, this integration facilitates significant cost reductions.…”

Wideband Low Phase-Noise Signal Generation Using Coaxial Resonator in Cascaded Phase Locked Loop

“…Combining both analog and digital functionalities, PLLs offer a balance between performance and cost. Recently, advancements in lithography have enabled the integration of PLL structures and high-frequency oscillators onto a single silicon wafer [6,10]. Leveraging established chip production processes, this integration facilitates significant cost reductions.…”

“…Recent research has explored this concept, focusing on significant improvements in phase noise (achieving exceptional results of −110 dBc/Hz at 100 kHz offset [10]) and fractional spur suppression (keeping them below −70 dBc [15]). However, to our knowledge, no existing work has addressed true wideband sweep operations applicable across diverse applications while simultaneously considering all of these challenges.…”

A Novel Fast-Locking ADPLL Based on Bisection Method

“…The traditional structure's locking time is related to output frequency range, filter's bandwidth, target frequency, and frequency resolution. The larger the output frequency range is, the smaller the bandwidth of the filter is, the farther the target frequency is from the initial frequency, and the higher frequency resolution of DCO is, resulting in longer locking time [9][10][11][12][13][14][15].…”